Abstract: A clock monitoring circuit includes: a sampling circuit suitable for sampling a monitoring target clock in synchronization with a sampling clock; a first counter circuit suitable for counting the number of times that the sampling circuit samples the monitoring target clock at a predetermined level; and a second counter circuit suitable for counting the number of times that the sampling circuit performs sampling.

Abstract: A clock generation circuit includes: a frequency detector suitable for generating an internal clock, and generating a counting signal indicating a toggling number of the internal clock during an activation period of an input clock; a control signal generator suitable for generating a plurality of period control signals based on a target signal and the counting signal, the target signal indicating a target frequency of an output clock; and a period controller suitable for generating the output clock based on the period control signals.

Abstract: A clock monitoring circuit includes: a sampling circuit suitable for sampling a monitoring target clock in synchronization with a sampling clock; a first counter circuit suitable for counting the number of times that the sampling circuit samples the monitoring target clock at a predetermined level; and a second counter circuit suitable for counting the number of times that the sampling circuit performs sampling.

Abstract: A clock generation circuit may include a first clock generator and a second clock generator. The first clock generator may generate a first output clock toggling in synchronization with a rising edge of a first input clock. The second clock generator may generate a second output clock based on a second input clock and the first output clock. The second output clock may have a level changing based on the first output clock, and may be generated at a rising edge of the second input clock.

Abstract: A clock generation circuit may include a first clock generator and a second clock generator. The first clock generator may generate a first output clock toggling in synchronization with a rising edge of a first input clock. The second clock generator may generate a second output clock based on a second input clock and the first output clock. The second output clock may have a level changing based on the first output clock, and may be generated at a rising edge of the second input clock.

Abstract: A semiconductor apparatus includes a pattern conversion circuit configured to generate conversion data in response to a monitoring enable signal, pattern select signals and parallel input data; a transmission circuit configured to output the conversion data as serial data in response to a plurality of clocks; a reception circuit configured to output the serial data as parallel output data in synchronization with the plurality of clocks; and a monitoring circuit configured to generate a result signal in response to the plurality of clocks, clock select signals and the serial data.

Abstract: A clock data recovery circuit may include: a phase comparison unit suitable for comparing input data with a phase of a multi-phase clock, and for generating an up/down signal corresponding to the comparison result; a filtering unit suitable for counting the up/down signal based on an upper threshold value and a lower threshold value, for setting, when an overflow occurs, the lower threshold value to an initial value for the count of the up/down signal, or when a underflow occurs, the upper threshold value to the initial value for the count of the up/down signal, and for generating a control code corresponding to one of the underflow and the overflow; and a phase rotating unit suitable for adjusting the phase of the multi-phase clock in response to the control code outputted from the filtering unit.

Abstract: A semiconductor system may include a first semiconductor device configured to output a command and receive data. The semiconductor system may include a second semiconductor device configured to generate a period signal, the period signals periodically toggled in response to the command, output the data in response to the period signal, and discharge the charges of an internal node if the period signal is not toggled during a predetermined section.

Abstract: An integrated circuit may include: a phase detector suitable for generating a delay control signal by comparing the phases of first and second clock signals to first and second target positions, a variable delay unit suitable for shifting the first and second clock signals to the first and second target positions, respectively, in response to the delay control signal, and a position controller suitable for varying the first and second target positions according to an operation mode.

Abstract: A semiconductor system may include a first semiconductor device configured to output a command and receive data. The semiconductor system may include a second semiconductor device configured to generate a period signal, the period signals periodically toggled in response to the command, output the data in response to the period signal, and discharge the charges of an internal node if the period signal is not toggled during a predetermined section.

Abstract: A delay circuit includes: a plurality of delay units that are serially coupled with each other in a form of loop and sequentially delay an input signal of the delay circuit; an input control unit that selects a delay unit to receive the input signal of the delay circuit among the plurality of the delay units; and an output control unit that controls an output signal of a predetermined delay unit among the plurality of the delay units to be outputted as an output signal of the delay circuit, when the output signal of the predetermined delay unit is enabled N times, where N is an integer equal to or greater than 0.

Abstract: A clock generation circuit may include a first clock generator, a second clock generator, and a common mode generator. The first clock generator may generate a multi-phase clock signal from a first clock signal. The second clock generator may generate a multi-phase clock signal from a second clock signal. The common mode generator may generate a reference voltage based on the first and second clock signals.

Abstract: A phase detection circuit includes a sampling signal generation circuit configured to generate a plurality of sampling signals in response to a plurality of phase change clocks having different phases and data; a charging voltage generation circuit configured to compare the plurality of sampling signals, and change a voltage level of one charging voltage between a first charging voltage and a second charging voltage; and a comparison circuit configured to compare voltage levels of the first and second charging voltages, and generate a result signal.

Abstract: A delay circuit includes: a plurality of delay units that are serially coupled with each other in a form of loop and sequentially delay an input signal of the delay circuit; an input control unit that selects a delay unit to receive the input signal of the delay circuit among the plurality of the delay units; and an output control unit that controls an output signal of a predetermined delay unit among the plurality of the delay units to be outputted as an output signal of the delay circuit, when the output signal of the predetermined delay unit is enabled N times, where N is an integer equal to or greater than 0.

Abstract: A clock generation circuit may be provided. The clock generation circuit may include a master DLL (Delay Locked Loop) circuit, a code divider and a slave DLL circuit. The master DLL may generate a phase pulse signal having a pulse width corresponding to one cycle of a clock signal, and may generate a delay control code corresponding to the phase pulse signal. The code divider may generate a divided delay control code corresponding to a predetermined time by dividing the delay control code. The slave DLL circuit may generate a delayed strobe signal by delaying a strobe signal according to the divided delay control code.

Abstract: A clock data recovery circuit may include: a phase comparison unit suitable for comparing input data with a phase of a multi-phase clock, and for generating an up/down signal corresponding to the comparison result; a filtering unit suitable for counting the up/down signal based on an upper threshold value and a lower threshold value, for setting, when an overflow occurs, the lower threshold value to an initial value for the count of the up/down signal, or when a underflow occurs, the upper threshold value to the initial value for the count of the up/down signal, and for generating a control code corresponding to one of the underflow and the overflow; and a phase rotating unit suitable for adjusting the phase of the multi-phase clock in response to the control code outputted from the filtering unit.

Abstract: A clock generation circuit may include a first clock generator, a second clock generator, and a common mode generator. The first clock generator may generate a multi-phase clock signal from a first clock signal. The second clock generator may generate a multi-phase clock signal from a second clock signal. The common mode generator may generate a reference voltage based on the first and second clock signals.

Abstract: A semiconductor system may include a first semiconductor device configured to output a command and receive data. The semiconductor system may include a second semiconductor device configured to generate a periodic signal, the periodic signals periodically toggled in response to the command, output the data in response to the periodic signal, and discharge the charges of an internal node if the periodic signal is not toggled during a predetermined section.

Abstract: A semiconductor apparatus includes a pattern conversion circuit configured to generate conversion data in response to a monitoring enable signal, pattern select signals and parallel input data; a transmission circuit configured to output the conversion data as serial data in response to a plurality of clocks; a reception circuit configured to output the serial data as parallel output data in synchronization with the plurality of clocks; and a monitoring circuit configured to generate a result signal in response to the plurality of clocks, clock select signals and the serial data.

Abstract: A phase detection circuit includes a sampling signal generation circuit configured to generate a plurality of sampling signals in response to a plurality of phase change clocks having different phases and data; a charging voltage generation circuit configured to compare the plurality of sampling signals, and change a voltage level of one charging voltage between a first charging voltage and a second charging voltage; and a comparison circuit configured to compare voltage levels of the first and second charging voltages, and generate a result signal.