Patents by Inventor Myung-Geun Song
Myung-Geun Song has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180174889Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.Type: ApplicationFiled: January 31, 2018Publication date: June 21, 2018Inventors: Young-Sang Youn, Myung-geun Song, Ji-hoon Cha, Jae-jik Baek, Bo-un Yoon, Jeong-nam Han
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Patent number: 9984921Abstract: A method of manufacturing a semiconductor device includes forming grooves in a first dielectric layer on a substrate, the first dielectric layer including a first part between the grooves, forming a first barrier layer and an interconnect layer in each groove, recessing the interconnect layer and the first barrier layer, forming a capping pattern on the recessed interconnect layer, etching at least a portion of the first part by a first etching process, sequentially etching the capping pattern and the at least a portion of the IMD part by a second etching process to form a trench, conformally forming a second barrier layer in the trench and on the recessed interconnection layer, and forming a second dielectric layer on the second barrier layer not to fill the trench such that an air gap is formed in the trench.Type: GrantFiled: November 3, 2017Date of Patent: May 29, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang Hoon Ahn, Jong Min Baek, Myung Geun Song, Woo Kyung You, Byung Kwon Cho, Byung Hee Kim, Na Ein Lee
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Patent number: 9984925Abstract: A semiconductor device, including a first fin-type pattern; a first gate spacer on the first fin-type pattern, intersecting the first fin-type pattern, and including an upper portion and a lower portion; a second gate spacer on the first fin-type pattern, intersecting the first fin-type pattern, and being spaced apart from the first gate spacer; a first trench defined by the first gate spacer and the second gate spacer; a first gate electrode partially filling the first trench; a first capping pattern on the first gate electrode and filling the first trench; and an interlayer insulating layer covering an upper surface of the capping pattern, a width of the upper portion of the first gate spacer decreasing as a distance from an upper surface of the first fin-type pattern increases, and an outer sidewall of the upper portion of the first gate spacer contacting the interlayer insulating layer.Type: GrantFiled: June 14, 2016Date of Patent: May 29, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong-Ho Jeon, Sang-Su Kim, Cheol Kim, Yong-Suk Tak, Myung-Geun Song, Gi-Gwan Park
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Publication number: 20180053685Abstract: A method of manufacturing a semiconductor device includes forming grooves in a first dielectric layer on a substrate, the first dielectric layer including a first part between the grooves, forming a first barrier layer and an interconnect layer in each groove, recessing the interconnect layer and the first barrier layer, forming a capping pattern on the recessed interconnect layer, etching at least a portion of the first part by a first etching process, sequentially etching the capping pattern and the at least a portion of the IMD part by a second etching process to form a trench, conformally forming a second barrier layer in the trench and on the recessed interconnection layer, and forming a second dielectric layer on the second barrier layer not to fill the trench such that an air gap is formed in the trench.Type: ApplicationFiled: November 3, 2017Publication date: February 22, 2018Inventors: Sang Hoon AHN, Jong Min BAEK, Myung Geun SONG, Woo Kyung YOU, Byung Kwon CHO, Byung Hee KIM, Na Ein LEE
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Patent number: 9812353Abstract: A method of manufacturing a semiconductor device includes forming grooves in a first dielectric layer on a substrate, the first dielectric layer including a first part between the grooves, forming a first barrier layer and an interconnect layer in each groove, recessing the interconnect layer and the first barrier layer, forming a capping pattern on the recessed interconnect layer, etching at least a portion of the first part by a first etching process, sequentially etching the capping pattern and the at least a portion of the IMD part by a second etching process to form a trench, conformally forming a second barrier layer in the trench and on the recessed interconnection layer, and forming a second dielectric layer on the second barrier layer not to fill the trench such that an air gap is formed in the trench.Type: GrantFiled: November 17, 2016Date of Patent: November 7, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang Hoon Ahn, Jong Min Baek, Myung Geun Song, Woo Kyung You, Byung Kwon Cho, Byung Hee Kim, Na Ein Lee
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Publication number: 20170301581Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.Type: ApplicationFiled: June 29, 2017Publication date: October 19, 2017Inventors: Young-Sang Youn, Myung-geun Song, Ji-hoon Cha, Jae-jik Baek, Bo-un Yoon, Jeong-nam Han
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Patent number: 9728535Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.Type: GrantFiled: March 2, 2016Date of Patent: August 8, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Young-sang Youn, Myung-geun Song, Ji-hoon Cha, Jae-jik Baek, Bo-un Yoon, Jeong-nam Han
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Publication number: 20170162431Abstract: A method of manufacturing a semiconductor device includes forming grooves in a first dielectric layer on a substrate, the first dielectric layer including a first part between the grooves, forming a first barrier layer and an interconnect layer in each groove, recessing the interconnect layer and the first barrier layer, forming a capping pattern on the recessed interconnect layer, etching at least a portion of the first part by a first etching process, sequentially etching the capping pattern and the at least a portion of the IMD part by a second etching process to form a trench, conformally forming a second barrier layer in the trench and on the recessed interconnection layer, and forming a second dielectric layer on the second barrier layer not to fill the trench such that an air gap is formed in the trench.Type: ApplicationFiled: November 17, 2016Publication date: June 8, 2017Inventors: Sang Hoon AHN, Jong Min BAEK, Myung Geun SONG, Woo Kyung YOU, Byung Kwon CHO, Byung Hee KIM, Na Ein LEE
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Publication number: 20170103916Abstract: A semiconductor device, including a first fin-type pattern; a first gate spacer on the first fin-type pattern, intersecting the first fin-type pattern, and including an upper portion and a lower portion; a second gate spacer on the first fin-type pattern, intersecting the first fin-type pattern, and being spaced apart from the first gate spacer; a first trench defined by the first gate spacer and the second gate spacer; a first gate electrode partially filling the first trench; a first capping pattern on the first gate electrode and filling the first trench; and an interlayer insulating layer covering an upper surface of the capping pattern, a width of the upper portion of the first gate spacer decreasing as a distance from an upper surface of the first fin-type pattern increases, and an outer sidewall of the upper portion of the first gate spacer contacting the interlayer insulating layer.Type: ApplicationFiled: June 14, 2016Publication date: April 13, 2017Inventors: Yong-Ho JEON, Sang-Su KIM, Cheol KIM, Yong-Suk TAK, Myung-Geun SONG, Gi-Gwan PARK
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Patent number: 9466697Abstract: Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.Type: GrantFiled: May 26, 2015Date of Patent: October 11, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Jine Park, Bo-Un Yoon, Jeong-Nam Han, Myung-Geun Song
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Publication number: 20160181243Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.Type: ApplicationFiled: March 2, 2016Publication date: June 23, 2016Inventors: Young-sang Youn, Myung-geun Song, Ji-hoon Cha, Jae-jik Baek, Bo-un Yoon, Jeong-nam Han
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Patent number: 9305825Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.Type: GrantFiled: February 7, 2014Date of Patent: April 5, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Young-sang Youn, Myung-geun Song, Ji-hoon Cha, Jae-jik Baek, Bo-un Yoon, Jeong-nam Han
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Publication number: 20150279991Abstract: Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.Type: ApplicationFiled: May 26, 2015Publication date: October 1, 2015Inventors: Sang-Jine PARK, Bo-Un YOON, Jeong-Nam HAN, Myung-Geun SONG
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Publication number: 20140322881Abstract: Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.Type: ApplicationFiled: July 9, 2014Publication date: October 30, 2014Inventors: Sang-Jine Park, Bo-Un Yoon, Jeong-Nam Han, Myung-Geun Song
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Patent number: 8859371Abstract: Methods for manufacturing a semiconductor device having a dual gate dielectric layer may include providing a substrate including first and second regions, forming a first gate dielectric layer having a first thickness on the substrate, forming an interlayer insulating layer including first and second trenches exposing the first gate dielectric layer in the first and second regions, forming a sacrificial layer on the interlayer insulating layer and bottoms of the first and second trenches, forming a sacrificial pattern exposing the first gate dielectric layer of the bottom of the first trench, removing the first gate dielectric layer of the bottom of the first trench, forming a second gate dielectric layer having a second thickness on the bottom of the first trench, removing the sacrificial pattern, and forming a gate electrode on each of the first and second gate dielectric layers.Type: GrantFiled: March 12, 2013Date of Patent: October 14, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Myung Geun Song, Ki-Hyung Ko, Hayoung Jeon, Boun Yoon, Jeongnam Han
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Publication number: 20140227857Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.Type: ApplicationFiled: February 7, 2014Publication date: August 14, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: YOUNG-SANG YOUN, MYUNG-GEUN SONG, JI-HOON CHA, JAE-JIK BAEK, BO-UN YOON, JEONG-NAM HAN
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Patent number: 8803248Abstract: Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.Type: GrantFiled: September 23, 2011Date of Patent: August 12, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Jine Park, Bo-Un Yoon, Jeong-Nam Han, Myung-Geun Song
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Publication number: 20130244414Abstract: Methods for manufacturing a semiconductor device having a dual gate dielectric layer may include providing a substrate including first and second regions, forming a first gate dielectric layer having a first thickness on the substrate, forming an interlayer insulating layer including first and second trenches exposing the first gate dielectric layer in the first and second regions, forming a sacrificial layer on the interlayer insulating layer and bottoms of the first and second trenches, forming a sacrificial pattern exposing the first gate dielectric layer of the bottom of the first trench, removing the first gate dielectric layer of the bottom of the first trench, forming a second gate dielectric layer having a second thickness on the bottom of the first trench, removing the sacrificial pattern, and forming a gate electrode on each of the first and second gate dielectric layers.Type: ApplicationFiled: March 12, 2013Publication date: September 19, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Myung Geun Song, Ki-Hyung Ko, Hayoung Jeon, Boun Yoon, Jeongnam Han
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Publication number: 20120104514Abstract: Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.Type: ApplicationFiled: September 23, 2011Publication date: May 3, 2012Inventors: Sang-Jine Park, Bo-Un Yoon, Jeong-Nam Han, Myung-Geun Song
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Publication number: 20090140198Abstract: Disclosed herein is a method of preparing a metal oxide suspension, which is advantageous due to the prevention of hydration and agglomeration of the metal oxide and a simple preparation process. The method of preparing a metal oxide suspension according to this invention includes preparing metal oxide, mixing the metal oxide with a solvent and a surface treating agent to obtain a mixture, and wet milling the mixture such that the metal oxide of the mixture has a nanoscale particle size and the metal oxide is uniformly dispersed in the mixture.Type: ApplicationFiled: April 18, 2006Publication date: June 4, 2009Applicants: SAMSUNG CORNING CO., LTD., SAMSUNG CORNING PRECISION GLASS CO., LTD.Inventors: Yoon-Gyu Lee, Jin-Ho Lee, Myung-Geun Song, Sin-Ae Song, Ja-Hoo Koo