Abstract: A method is presented for forming a layout of a MOSFET (metal oxide semiconductor field effect transistor) circuit. The method includes forming a plurality of gate conductors, forming a plurality of active areas, and forming at least one gate contact (CB contact) within an active region of the plurality of active regions. The method further includes placing a marker over the at least one gate contact to identify a location of the at least one gate contact. Additionally, a distance between the at least one gate contact and at least one TS contact is optimized based on device specifications.

Abstract: A method is presented for forming a layout of a MOSFET (metal oxide semiconductor field effect transistor) circuit. The method includes forming a plurality of gate conductors, forming a plurality of active areas, and forming at least one gate contact (CB contact) within an active region of the plurality of active regions. The method further includes placing a marker over the at least one gate contact to identify a location of the at least one gate contact. Additionally, a distance between the at least one gate contact and at least one TS contact is optimized based on device specifications.

Abstract: A technique relates to a method of optimizing self-aligned double patterning. Predefined locations for required metal cuts are provided in order to form metal wires from metal fills that have been cut. Extended locations for extended metal cuts are provided in order to cut adjacent metal fills. The adjacent metal fills are the metal fills that are adjacent to the predefined locations for the required metal cuts, and the extended metal cuts extend beyond the required metal cuts. The required metal cuts into the metal fills are performed and the extended metal cuts into the adjacent metal fills are performed.

Abstract: A technique relates to a method of optimizing self-aligned double patterning. Predefined locations for required metal cuts are provided in order to form metal wires from metal fills that have been cut. Extended locations for extended metal cuts are provided in order to cut adjacent metal fills. The adjacent metal fills are the metal fills that are adjacent to the predefined locations for the required metal cuts, and the extended metal cuts extend beyond the required metal cuts. The required metal cuts into the metal fills are performed and the extended metal cuts into the adjacent metal fills are performed.

Abstract: Device structures and fabrication methods for a fin-type field-effect transistor. A first contact, a second contact, and a gate electrode are formed on a fin comprised of a semiconductor material. The second contact is spaced along a length of the fin from the first contact. The gate electrode is positioned along the length of the fin between the first contact and the second contact.

Abstract: Methods form complementary metal oxide semiconductor (CMOS) devices that include a first transistor and a complementary second transistor, and an output connected to the first transistor and the second transistor. The first transistor includes a first channel region, a first back gate, a first delay element between the output and the first back gate, and a first back gate insulator separating the first back gate from the first channel region. The second transistor includes a second channel region, a second back gate, a second delay element between the output and the second back gate, and a second back gate insulator separating the second back gate from the second channel region. The first delay element, the first back gate insulator, and the first channel region form a first resistor-capacitor (RC) circuit, and the second delay element, the second back gate insulator, and the second channel region form a second RC circuit.

Abstract: A fin structure includes an optional doped well, a disposable single crystalline semiconductor material portion, and a top semiconductor portion formed on a substrate. A disposable gate structure straddling the fin structure is formed, and end portions of the fin structure are removed to form end cavities. Doped semiconductor material portions are formed on sides of a stack of the disposable single crystalline semiconductor material portion and a channel region including the top semiconductor portion. The disposable single crystalline semiconductor material portion may be replaced with a dielectric material portion after removal of the disposable gate structure or after formation of the stack. The gate cavity is filled with a gate dielectric and a gate electrode. The channel region is stressed by the doped semiconductor material portions, and is electrically isolated from the substrate by the dielectric material portion.

Abstract: A FinFET semiconductor device fabrication process includes forming a plurality of FinFET fins upon a semiconductor substrate, forming a first dielectric layer upon the semiconductor substrate so that an upper surface of the first dielectric layer is coplanar with upper surfaces of the FinFET fins, forming a plurality of dummy gates upon the FinFET fins and the first dielectric layer orthogonal to the FinFET fins, revealing the FinFET fins by removing first portions of the first dielectric layer from source-drain regions, removing the dummy gates, and subsequent to the removal of the dummy gates, revealing the FinFET fins by removing second portions of the first dielectric layer from channel regions.

Abstract: A FinFET semiconductor device fabrication process includes forming a plurality of FinFET fins upon a semiconductor substrate, forming a first dielectric layer upon the semiconductor substrate so that an upper surface of the first dielectric layer is coplanar with upper surfaces of the FinFET fins, forming a plurality of dummy gates upon the FinFET fins and the first dielectric layer orthogonal to the FinFET fins, revealing the FinFET fins by removing first portions of the first dielectric layer from source-drain regions, removing the dummy gates, and subsequent to the removal of the dummy gates, revealing the FinFET fins by removing second portions of the first dielectric layer from channel regions.

Abstract: A first silicon-germanium alloy layer is formed on a semiconductor substrate including silicon. A stack of a first silicon layer and a second silicon-germanium alloy layer is formed over a first region of the first silicon-germanium alloy layer, and a second silicon layer thicker than the first silicon layer is formed over a second region of the first silicon-germanium alloy layer. At least one first semiconductor fin is formed in the first region, and at least one second semiconductor fin is formed in the second region. Remaining portions of the first silicon layer are removed to provide at least one silicon-germanium alloy fin in the first region, while at least one silicon fin is provided in the second region. Fin field effect transistors can be formed on the at least one silicon-germanium alloy fin and the at least one silicon fin.

Abstract: A fin structure includes an optional doped well, a disposable single crystalline semiconductor material portion, and a top semiconductor portion formed on a substrate. A disposable gate structure straddling the fin structure is formed, and end portions of the fin structure are removed to form end cavities. Doped semiconductor material portions are formed on sides of a stack of the disposable single crystalline semiconductor material portion and a channel region including the top semiconductor portion. The disposable single crystalline semiconductor material portion may be replaced with a dielectric material portion after removal of the disposable gate structure or after formation of the stack. The gate cavity is filled with a gate dielectric and a gate electrode. The channel region is stressed by the doped semiconductor material portions, and is electrically isolated from the substrate by the dielectric material portion.

Abstract: A fin structure includes an optional doped well, a disposable single crystalline semiconductor material portion, and a top semiconductor portion formed on a substrate. A disposable gate structure straddling the fin structure is formed, and end portions of the fin structure are removed to form end cavities. Doped semiconductor material portions are formed on sides of a stack of the disposable single crystalline semiconductor material portion and a channel region including the top semiconductor portion. The disposable single crystalline semiconductor material portion may be replaced with a dielectric material portion after removal of the disposable gate structure or after formation of the stack. The gate cavity is filled with a gate dielectric and a gate electrode. The channel region is stressed by the doped semiconductor material portions, and is electrically isolated from the substrate by the dielectric material portion.

Abstract: A first silicon-germanium alloy layer is formed on a semiconductor substrate including silicon. A stack of a first silicon layer and a second silicon-germanium alloy layer is formed over a first region of the first silicon-germanium alloy layer, and a second silicon layer thicker than the first silicon layer is formed over a second region of the first silicon-germanium alloy layer. At least one first semiconductor fin is formed in the first region, and at least one second semiconductor fin is formed in the second region. Remaining portions of the first silicon layer are removed to provide at least one silicon-germanium alloy fin in the first region, while at least one silicon fin is provided in the second region. Fin field effect transistors can be formed on the at least one silicon-germanium alloy fin and the at least one silicon fin.

Abstract: A fin structure includes an optional doped well, a disposable single crystalline semiconductor material portion, and a top semiconductor portion formed on a substrate. A disposable gate structure straddling the fin structure is formed, and end portions of the fin structure are removed to form end cavities. Doped semiconductor material portions are formed on sides of a stack of the disposable single crystalline semiconductor material portion and a channel region including the top semiconductor portion. The disposable single crystalline semiconductor material portion may be replaced with a dielectric material portion after removal of the disposable gate structure or after formation of the stack. The gate cavity is filled with a gate dielectric and a gate electrode. The channel region is stressed by the doped semiconductor material portions, and is electrically isolated from the substrate by the dielectric material portion.

Abstract: A semiconductor includes: a first field-effect transistor (FET); and a second FET of similar polarity to the first FET, wherein a body of the first FET is electrically coupled to a body of the second FET, and a source of the first FET is electrically coupled to a source of the second FET, such that a body voltage of the second FET controls a body voltage of the first FET.

Abstract: A semiconductor includes: a first field-effect transistor (FET); and a second FET of similar polarity to the first FET, wherein a body of the first FET is electrically coupled to a body of the second FET, and a source of the first FET is electrically coupled to a source of the second FET, such that a body voltage of the second FET controls a body voltage of the first FET.

Abstract: A semiconductor device includes: a first field-effect transistor (FET); and a second FET of similar polarity to the first FET, wherein a body of the first FET is electrically coupled to a body of the second FET, and a source of the first FET is electrically coupled to a source of the second FET, such that a body voltage of the second FET controls a body voltage of the first FET.

Abstract: Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.

Abstract: A semiconductor device is disclosed. The structure includes: a first field-effect transistor (FET); and a second FET of similar polarity to the first FET, wherein a body of the first FET is electrically coupled to a body of the second FET, and a source of the first FET is electrically coupled to a source of the second FET, such that a body voltage of the second FET controls a body voltage of the first FET.

Abstract: Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.