Abstract: A semiconductor package includes a frame having a wiring structure and having a recess portion, a semiconductor chip having an active surface with a connection pad disposed thereon and disposed in the recess portion, an encapsulant sealing the semiconductor chip, and a redistribution layer having a first via connected to the connection and a second via connected to a portion of the wiring structure. The semiconductor chip includes a protective insulating film disposed on the active surface and having an opening exposing a region of the connection pad, and a redistribution capping layer connected to the region of the connection pad and extending onto the protective insulating film, and a surface of the redistribution capping layer is substantially the same level as a surface of the portion of the wiring structure, exposed from the first surface.

Abstract: A semiconductor package includes a frame having first and second through-portions, first and second semiconductor chips, respectively in the first and second through-portions, each having a first surface, on which a connection pad is disposed, a first encapsulant covering at least a portion of the first and second semiconductor chips, a first connection member on the first and second semiconductor chips including a first redistribution layer electrically connected to the connection pads of the first and second semiconductor chips and a heat dissipation pattern layer, at least one passive component above the first semiconductor chip on the first connection member, and at least one heat dissipation structure above the second semiconductor chip on the first connection member and connected to the heat dissipation pattern layer.

Abstract: There are provided an inductor and a method of manufacturing the same. The inductor includes: a body including a coil part; and cover parts disposed on upper and lower surfaces of the body. The coil part includes a plurality of through-vias penetrating through the upper and lower surfaces of the body and connection patterns disposed on the upper and lower surfaces of the body, disposed in the cover parts, and connecting the plurality of through-vias to each other.

Abstract: A fan-out semiconductor package includes: a core member having a first through-hole and including a dummy metal layer; a first semiconductor chip disposed in the first through-hole and having a first active surface having first connection pads disposed thereon and a first inactive surface opposing the first active surface; a first encapsulant covering at least portions of the core member and the first semiconductor chip and filling at least portions of the first through-hole; and a first connection member disposed on the core member and the first active surface of the first semiconductor chip and including a first redistribution layer electrically connected to the first connection pads, wherein the dummy metal layer is electrically insulated from signal patterns of the first redistribution layer.

Abstract: A semiconductor package includes a support member including a resin body having a first surface and a second surface opposing each other and having a cavity, and at least one passive component embedded in the resin body and having a connection terminal exposed from the first surface; a first connection member disposed on the first surface of the resin body, and having a first redistribution layer on the first insulating layer and connected to the connection terminal; a second connection member disposed on the first connection member and covering the cavity, and having a second redistribution layer on the second insulating layer and connected to the first redistribution layer; and a semiconductor chip disposed on the second connection member in the cavity.

Abstract: A semiconductor package includes a semiconductor chip having connection pads on one surface thereof, a first encapsulant covering at least portions of the semiconductor chip, and a connection structure disposed on the one surface of the semiconductor chip and including one or more redistribution layers electrically connected to the connection pads. A wiring structure is disposed on one surface of the first encapsulant opposing another surface of the first encapsulant facing towards the connection structure. The wiring structure has a passive component embedded therein, and includes one or more wiring layers electrically connected to the passive component. The one or more redistribution layers and the one or more wiring layers are electrically connected to each other.

Abstract: A semiconductor package may include a frame including an insulation layer having a cavity formed in a lower surface of the insulation layer, a first post and a second post spaced apart from the cavity, and a metal plate disposed on an upper side of the cavity; a semiconductor chip having a first surface on which a connection pad is disposed and a second surface opposing the first surface; an encapsulant covering at least a portion of the semiconductor chip; and a connection structure disposed on the frame and the first surface of the semiconductor chip, and including one or more redistribution layers. The first post is electrically connected to the wiring layer of the frame and the redistribution layer of the connection structure, and the second post is spaced apart from the first post.

Abstract: A semiconductor package may include a frame including an insulation layer having a cavity formed in a lower surface of the insulation layer, a first post and a second post spaced apart from the cavity, and a metal plate disposed on an upper side of the cavity; a semiconductor chip having a first surface on which a connection pad is disposed and a second surface opposing the first surface; an encapsulant covering at least a portion of the semiconductor chip; and a connection structure disposed on the frame and the first surface of the semiconductor chip, and including one or more redistribution layers. The first post is electrically connected to the wiring layer of the frame and the redistribution layer of the connection structure, and the second post is spaced apart from the first post.

Abstract: A semiconductor package includes a first connection member including a first redistribution layer, a first frame disposed on the first connection member, a first semiconductor chip disposed on a first through-portion and having a connection pad, a first encapsulant covering a portion of each of the first frame and the first semiconductor chip and filling at least a portion of the first through-portion, a second connection member disposed on the first encapsulant and including a second redistribution layer, a second semiconductor chip disposed on the second connection member and having a second connection pad, a second encapsulant covering a portion of the second semiconductor chip, and a first through-via penetrating through the first frame, the first encapsulant, and a portion of the first connection member, and electrically connecting the first and second redistribution layers to each other.

Abstract: A semiconductor package includes a semiconductor chip having connection pads on one surface thereof, a first encapsulant covering at least portions of the semiconductor chip, and a connection structure disposed on the one surface of the semiconductor chip and including one or more redistribution layers electrically connected to the connection pads. A wiring structure is disposed on one surface of the first encapsulant opposing another surface of the first encapsulant facing towards the connection structure. The wiring structure has a passive component embedded therein, and includes one or more wiring layers electrically connected to the passive component. The one or more redistribution layers and the one or more wiring layers are electrically connected to each other.

Abstract: A fan-out semiconductor package includes: a core member having a first through-hole and including a dummy metal layer; a first semiconductor chip disposed in the first through-hole and having a first active surface having first connection pads disposed thereon and a first inactive surface opposing the first active surface; a first encapsulant covering at least portions of the core member and the first semiconductor chip and filling at least portions of the first through-hole; and a first connection member disposed on the core member and the first active surface of the first semiconductor chip and including a first redistribution layer electrically connected to the first connection pads, wherein the dummy metal layer is electrically insulated from signal patterns of the first redistribution layer.

Abstract: A semiconductor package includes a connection structure including a first insulation layer, a second insulation layer, first and second wiring layers, and first and second connection vias. A core structure including a core member is on the first insulation layer. A first through-hole passes through the core member. Passive components are on the first insulation layer in the first through-hole and connected to the first wiring layer through the first connection via. A first encapsulant covers at least a portion of the passive components. A second through-hole passes through the core structure and the first insulation layer. A semiconductor chip is on the second insulation layer in the second through-hole and is connected to the second wiring layer through the second connection via. A second encapsulant covers at least a portion of the semiconductor chip.

Abstract: A multilayer seed pattern inductor includes a magnetic body and an internal coil part. The magnetic body contains a magnetic material. The internal coil part is embedded in the magnetic body and includes connected coil conductors disposed on two opposing surfaces of an insulating substrate. Each of the coil conductors includes a seed pattern formed of at least two layers, a surface coating layer covering the seed pattern, and an upper plating layer formed on an upper surface of the surface coating layer.

Abstract: A coil electronic component includes a body portion and an external electrode. The body portion includes a coil layer and a reinforcing layer disposed on at least one of an upper portion and a lower portion of the coil layer. The external electrode is disposed on an outer surface of the body portion. The coil layer includes an insulating layer, a coil pattern, and a first conductivity type via penetrating through the insulating layer to be connected to the coil pattern, and the reinforcing layer has a higher degree of rigidity than the insulating layer.

Abstract: A semiconductor package includes a connection structure including an insulating layer, a redistribution layer disposed on the insulating layer, and a connection via penetrating through the insulating layer and connected to the redistribution layer, a frame disposed on the connection structure and having a through-hole, a semiconductor chip disposed in the through-hole on the connection structure and having a connection pad disposed to face the connection structure, and a passive component disposed on the frame.

Abstract: A semiconductor package includes a core structure having a first through-hole and including a frame having an opening, a passive component disposed in the opening, a first encapsulant covering the frame and the passive component, a first metal layer disposed on an inner surface of the first through-hole, and a second metal layer disposed on an inner surface of the opening; a first semiconductor chip disposed in the first through-hole and having a first connection pad; a second encapsulant covering the core structure and the first semiconductor chip; a connection structure disposed on the core structure and the first semiconductor chip and including a redistribution layer; and a metal pattern layer disposed on the second encapsulant. The first and second metal layers are connected to the metal pattern layer through first and second metal vias having heights different from each other.

Abstract: A coil electronic component includes: a plurality of coil layers including, respectively, coil patterns and connection patterns disposed outside the coil patterns and forming a stacking structure; conductive vias connecting the coil patterns formed on different levels to each other; and external electrodes electrically connected to the plurality of coil layers. The coil patterns of at least two of the plurality of coil layers may have the same shape and be electrically connected to each other in parallel.

Abstract: A multilayer seed pattern inductor includes a magnetic body and an internal coil part. The magnetic body contains a magnetic material. The internal coil part is embedded in the magnetic body and includes connected coil conductors disposed on two opposing surfaces of an insulating substrate. Each of the coil conductors includes a seed pattern formed of at least two layers, a surface coating layer covering the seed pattern, and an upper plating layer formed on an upper surface of the surface coating layer.

Abstract: A fan-out semiconductor package includes a core member having a through-hole in which a semiconductor chip is disposed. The semiconductor chip has an active surface having connection pads disposed thereon and an inactive surface opposing the active surface. An encapsulant encapsulates at least a portion of the semiconductor chip. A connection member is disposed on the active surface of the semiconductor chip and includes a redistribution layer electrically connected to the connection pads of the semiconductor chip. A passivation layer is disposed on the connection member. The fan-out semiconductor package further has a slot spaced part from the through-hole and penetrating through at least a portion of the core member or the passivation layer.

Abstract: A coil electronic component includes: a plurality of stacked coil layers each including coil patterns including anisotropic plating layers; conductive vias connecting the coil patterns formed on different coil layers to each other; and external electrodes electrically connected to the plurality of coil layers.