Abstract: A semiconductor package includes a support member including a resin body having a first surface and a second surface opposing each other and having a cavity, and at least one passive component embedded in the resin body and having a connection terminal exposed from the first surface; a first connection member disposed on the first surface of the resin body, and having a first redistribution layer on the first insulating layer and connected to the connection terminal; a second connection member disposed on the first connection member and covering the cavity, and having a second redistribution layer on the second insulating layer and connected to the first redistribution layer; and a semiconductor chip disposed on the second connection member in the cavity.

Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion having a stopper layer; a semiconductor chip having connection pads and disposed in the recess portion so that an inactive surface is connected to the stopper layer; a first encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; an electronic component disposed on the other surface of the frame opposing one surface of the frame in which the semiconductor chip is disposed; a second encapsulant covering at least portions of the electronic component; and a connection member disposed on the frame and an active surface of the semiconductor chip and including a redistribution layer, wherein the connection pads and the electronic component are electrically connected to each other through the wiring layers and the redistribution layer.

Abstract: A coil electronic component includes: a plurality of stacked coil layers each including coil patterns including anisotropic plating layers; conductive vias connecting the coil patterns formed on different coil layers to each other; and external electrodes electrically connected to the plurality of coil layers.

Abstract: A multilayered substrate in accordance with an aspect of the present disclosure may include an insulating layer, a conductive pattern embedded, at least partially, in the insulating layer, and a bump being electrically connected to the conductive pattern and penetrating the insulating layer. The bump may include a low melting point metal layer having a melting point lower than a melting point of the conductive pattern and a high melting point metal layer having a melting point higher than the melting point of the low melting point metal layer and having a latitudinal cross-sectional area smaller than a latitudinal cross-sectional area of the low melting point metal layer.

Abstract: A fan-out semiconductor package includes: a core member having a first through-hole and including a dummy metal layer; a first semiconductor chip disposed in the first through-hole and having a first active surface having first connection pads disposed thereon and a first inactive surface opposing the first active surface; a first encapsulant covering at least portions of the core member and the first semiconductor chip and filling at least portions of the first through-hole; and a first connection member disposed on the core member and the first active surface of the first semiconductor chip and including a first redistribution layer electrically connected to the first connection pads, wherein the dummy metal layer is electrically insulated from signal patterns of the first redistribution layer.

Abstract: A semiconductor package includes a connection structure including a first insulation layer, a second insulation layer, first and second wiring layers, and first and second connection vias. A core structure including a core member is on the first insulation layer. A first through-hole passes through the core member. Passive components are on the first insulation layer in the first through-hole and connected to the first wiring layer through the first connection via. A first encapsulant covers at least a portion of the passive components. A second through-hole passes through the core structure and the first insulation layer. A semiconductor chip is on the second insulation layer in the second through-hole and is connected to the second wiring layer through the second connection via. A second encapsulant covers at least a portion of the semiconductor chip.

Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip disposed in the recess portion, and having connection pads, an active surface on which the connection pads are disposed, and an inactive surface opposing the active surface and disposed on the stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; and a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connecting the plurality of wiring layers of the frame and the connection pads of the semiconductor chip to each other. The active surface of the semiconductor chip and an upper surface of the encapsulant have a step portion therebetween.

Abstract: A coil component includes: a body including a magnetic material, coil pattern layers disposed in the magnetic material, a core portion surrounded by the coil pattern layers, and an insulating layer disposed in the core portion and between adjacent coil pattern layers among the coil pattern layers, wherein each of the coil pattern layers comprises a spiral-shaped pattern; and an external electrode disposed on the body.

Abstract: A coil electronic component includes: a plurality of stacked coil layers each including coil patterns including anisotropic plating layers; conductive vias connecting the coil patterns formed on different coil layers to each other; and external electrodes electrically connected to the plurality of coil layers.

Abstract: A circuit board is disclosed. In addition to insulating layers, the circuit board includes a structure for heat transfer that includes a first layer that is formed of graphite or graphene, a second layer that is formed of metallic material and disposed on one surface of the first layer, and a third layer that is formed of metallic material and disposed on the other surface of the first layer, and at least a portion of the structure for heat transfer is inserted into an insulation layer. Such a circuit board provides improved heat management. Also disclosed is a method of manufacturing the circuit board.

Abstract: A printed circuit board and a method of manufacturing the same are provided. The printed circuit board includes an inner layer including at least one insulating layer and wiring parts, and outer layers disposed on opposing sides of the inner layer, the outer layers including reinforcing layers and wiring parts, the reinforcing layers having a greater degree of rigidity than the insulating layer.

Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip having connection pads and disposed in the recess portion so that an inactive surface is disposed on the stopper layer; first metal bumps disposed on the connection pads; an encapsulant covering at least portions of each of the frame, the semiconductor chip, and the first metal bumps and filling at least portions of the recess portion; a connection member disposed on the frame and an active surface of the semiconductor chip and including a redistribution layer electrically connecting the wiring layers and the connection pads to each other; and a first blocking structure disposed on walls of the recess portion to surround side surfaces of the semiconductor chip.

Abstract: A fan-out semiconductor package includes a core member having a through-hole in which a semiconductor chip is disposed. The semiconductor chip has an active surface having connection pads disposed thereon and an inactive surface opposing the active surface. An encapsulant encapsulates at least a portion of the semiconductor chip. A connection member is disposed on the active surface of the semiconductor chip and includes a redistribution layer electrically connected to the connection pads of the semiconductor chip. A passivation layer is disposed on the connection member. The fan-out semiconductor package further has a slot spaced part from the through-hole and penetrating through at least a portion of the core member or the passivation layer.

Abstract: A multilayer capacitor includes a body including dielectric layers and first and second internal electrodes alternately disposed with dielectric layers interposed therebetween. First and second external electrodes are on the body and connected to the first and second internal electrodes, respectively. The first and second internal electrodes are plating layers. A manufacturing method of a multilayer capacitor includes preparing a plurality of laminated sheets including internal electrodes, dummy electrodes, and dielectric layers. The plurality of laminated sheets, and covers on and below the laminated sheets, are simultaneously stacked and then cured to prepare a cured product. The cured product is then diced depending on the size of the capacitor to prepare a body where the internal electrodes and the dummy electrodes are partially exposed. External electrodes are formed on external surfaces of the body using the dummy electrodes as seeds in a plating method.

Abstract: Disclosed is an inductor device and method of manufacturing the same. The inductor device includes an insulating layer, a coil pattern formed on two opposing surfaces of the insulating layer, a first insulating film and a second insulating film formed with different insulating materials on the coil pattern, and a magnetic member formed to enclose the insulating layer, the coil pattern and the first and the second insulating films. By forming thin dual insulating films having a high adhesive strength and breaking strength on an inductor coil, it is possible to improve Ls characteristics of the inductor device and increase the inductance.

Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion having a stopper layer; a semiconductor chip having connection pads and disposed in the recess portion so that an inactive surface is connected to the stopper layer; a first encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; an electronic component disposed on the other surface of the frame opposing one surface of the frame in which the semiconductor chip is disposed; a second encapsulant covering at least portions of the electronic component; and a connection member disposed on the frame and an active surface of the semiconductor chip and including a redistribution layer, wherein the connection pads and the electronic component are electrically connected to each other through the wiring layers and the redistribution layer.

Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion having a stopper layer; a semiconductor chip having connection pads and disposed in the recess portion so that an inactive surface is connected to the stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; and a connection member disposed on the frame and an active surface of the semiconductor chip and including a redistribution layer electrically connecting the wiring layers of the frame and the connection pads of the semiconductor chip to each other. A lowermost wiring layer of the wiring layers is embedded in the frame and has a lower surface exposed from a lowermost insulating layer of the frame.

Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip disposed in the recess portion, and having connection pads, an active surface on which the connection pads are disposed, and an inactive surface opposing the active surface and disposed on the stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; and a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connecting the plurality of wiring layers of the frame and the connection pads of the semiconductor chip to each other. The active surface of the semiconductor chip and an upper surface of the encapsulant have a step portion therebetween.

Abstract: The present disclosure relates to a semiconductor package, and more particularly, to a fan-out semiconductor package in which connection terminals may extend outwardly of a region in which a semiconductor chip is disposed. In the fan-out semiconductor package, a circuit density of a redistribution layer may be increased even in a limited area.

Abstract: A circuit board includes an insulating part including insulating layers, metal layers disposed on the insulating layers, vias each passing through at least one insulating layer among the insulating layers and connecting together at least two metal layers among the metal layers; a first thermally conductive structure including a thermally conductive material, at least a part of the thermally conductive structure being inserted into the insulating part, a first via having one surface contacting the first thermally conductive structure, a first metal pattern contacting another surface of the first via, a first bonding member connected to the first metal pattern, and pads to which a first electronic component is connected on an outermost surface of a metal layer disposed on an outermost surface of the insulating part, the pads being at least in a first region and a second region having a higher temperature than the first region.