Patents by Inventor N. Lay

N. Lay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180365180
    Abstract: Embodiments include a technique for management of data transactions, where the technique includes receiving, at a link interface, a packet from an I/O device, wherein the packet includes address information, and performing, by a host bridge, an address translation for the address information included in the packet. The technique also includes responsive to performing the address translation, determining a target page associated with a translated address of the packet is for at least one of a payload target page or a signaling target page, and appending a flag to a command based at least in part on the target page being associated with the translated address of the packet. The technique includes transmitting the command to an ordering controller for ordering the packet.
    Type: Application
    Filed: June 15, 2017
    Publication date: December 20, 2018
    Inventors: David F. Craddock, Sascha Junghans, Matthias Klein, Eric N. Lais
  • Publication number: 20180365182
    Abstract: Embodiments include a technique for management of data transactions, where the technique includes receiving, at a link interface, a packet from an I/O device, wherein the packet includes address information, and performing, by a host bridge, an address translation for the address information included in the packet. The technique also includes responsive to performing the address translation, determining a target page associated with a translated address of the packet is for at least one of a payload target page or a signaling target page, and appending a flag to a command based at least in part on the target page being associated with the translated address of the packet. The technique includes transmitting the command to an ordering controller for ordering the packet.
    Type: Application
    Filed: November 9, 2017
    Publication date: December 20, 2018
    Inventors: David F. Craddock, Sascha Junghans, Matthias Klein, Eric N. Lais
  • Publication number: 20180357171
    Abstract: A synchronous input/output (I/O) computing system includes a processor and a memory unit that stores program instructions. The system purges one or more address translation entries in response to the processor executing the program instructions to issue, via an operating system running on the synchronous I/O computing system, a synchronous I/O command indicating a request to perform a transaction. The program instructions further command the operating system to select a device table entry from a device table, load the entry into the DTC, request required address translation entries, install the required address translation entries in the address translation cache, and transfer data packets corresponding to the transaction. The program instructions further command the operating system to automatically purge the address translation cache entries associated with a transaction in response to detect that the transaction is completed.
    Type: Application
    Filed: August 14, 2018
    Publication date: December 13, 2018
    Inventors: David F. Craddock, Matthias Klein, Eric N. Lais
  • Patent number: 10133691
    Abstract: A computer-implemented method for synchronous input/output (I/O) cache line padding is described. The cache line padding occurs between a server having a processor executing an operating system and a recipient control unit. The method can include receiving, via the processor at the recipient control unit, a partial line direct memory access (DMA) write request; fetching, via the processor, a device table entry (DTE) associated with the partial line DMA write request; determining, via the processor, a cache line size for a synchronous input/output (I/O) cache line; and writing a full cache line DMA write request by padding, via the processor, the partial line DMA write request with a padded portion, where the padded portion is based on the cache line size.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: November 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Scott A. Brewer, David F. Craddock, Matthew J. Kalos, Matthias Klein, Eric N. Lais
  • Patent number: 10133694
    Abstract: Embodiments of the present disclosure use vendor defined messages (VDMs) to send high priority information (e.g., cache writebacks) on a designated channel that is separate from a channel used for other commands (e.g., normal memory write commands). By using VDMs and a designated channel to send cache writebacks, the cache writebacks will not be blocked by normal memory write commands. For example, an endpoint device may encode cache writebacks as VDMs to be sent to a root complex. The root complex may store the VDMs in a dedicated VDM buffer and send the VDMs on a dedicated VDM channel.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: November 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Eric N. Lais, Adalberto G. Yanes
  • Patent number: 10095620
    Abstract: A synchronous input/output (I/O) computing system includes a processor and a memory unit that stores program instructions. The system purges one or more address translation entries in response to the processor executing the program instructions to issue, via an operating system running on the synchronous I/O computing system, a synchronous I/O command indicating a request to perform a transaction. The program instructions further command the operating system to select a device table entry from a device table, load the entry into the DTC, request required address translation entries, install the required address translation entries in the address translation cache, and transfer data packets corresponding to the transaction. The program instructions further command the operating system to automatically purge the address translation cache entries associated with a transaction in response to detect that the transaction is completed.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: October 9, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David F. Craddock, Matthias Klein, Eric N. Lais
  • Publication number: 20180203817
    Abstract: A computing system includes a processor and a memory unit that stores program instructions. The system purges an entry from an address translation cache in response to the processor executing the program instructions to perform issuing, via an operating system running on the computing system, a command indicating a request to perform an I/O transaction requiring a translation entry. A host bridge monitors a total data length of the address translation entry to be transferred during the I/O transaction. An address translation entry is selected from an address translation table, loaded into the address translation cache, and data corresponding to the I/O transaction is transferred using the selected address translation entry. The host bridge automatically purges the selected address translation entry from the address translation cache in response to determining the transferred amount of data matches the total data length for the address translation entry.
    Type: Application
    Filed: March 16, 2018
    Publication date: July 19, 2018
    Inventors: Matthias Klein, Eric N. Lais, Darwin W. Norton, JR.
  • Patent number: 9965350
    Abstract: A method of maintaining a device table cache (DTC) included in a Synchronous input/output (I/O) computing system includes issuing, with a processor executing an operating system running on the Synchronous I/O computing system, a Synchronous I/O command indicating a request to perform a device table entry transaction including a plurality of device table entries. The method also includes determining, with a host bridge processor, based on device table information, whether the device table entry transaction is associated with a cyclic redundancy check (CRC) transaction, and pinning, with the host bridge processor, a device table entry from a device table based on the determination.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: May 8, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David Craddock, Matthias Klein, Eric N. Lais, Harry M. Yudenfriend
  • Publication number: 20180095887
    Abstract: A method of maintaining a device table cache (DTC) included in a Synchronous input/output (I/O) computing system includes issuing, with a processor executing an operating system running on the Synchronous I/O computing system, a Synchronous I/O command indicating a request to perform a device table entry transaction including a plurality of device table entries. The method also includes determining, with a host bridge processor, based on device table information, whether the device table entry transaction is associated with a cyclic redundancy check (CRC) transaction, and pinning, with the host bridge processor, a device table entry from a device table based on the determination.
    Type: Application
    Filed: September 30, 2016
    Publication date: April 5, 2018
    Inventors: David Craddock, Matthias Klein, Eric N. Lais, Harry M. Yudenfriend
  • Publication number: 20180089114
    Abstract: A system includes a cut-through buffer operable to be asynchronously read while being written at different clock frequencies. The system also includes a controller operatively connected to the cut-through buffer. The controller is operable to write one or more values into the cut-through buffer in a first clock domain and compare a number of values written into the cut-through buffer to a notification threshold. A notification indicator is passed from the first clock domain to a second clock domain based on determining that the number of values written into the cut-through buffer meets the notification threshold. Based on receiving the notification indicator, the cut-through buffer is read from the second clock domain continuously without pausing until the one or more values are retrieved and any additional values written to the cut-through buffer during the reading of the one or more values are retrieved.
    Type: Application
    Filed: September 27, 2016
    Publication date: March 29, 2018
    Inventors: Jeffrey C. Hanscom, Eric N. Lais, John M. Pritz
  • Publication number: 20180089124
    Abstract: A system includes an input/output adapter operable to receive a plurality of packets in a single clock cycle. The system includes a controller operatively connected to the input/output adapter. The controller is operable to receive a first packet at a data link layer and determine a state of a first output indicator to maintain packet ordering. Based on determining that a first receiver formatting interface is selected by the first output indicator, the controller performs an alignment adjustment and output of the first packet by the first receiver formatting interface. Based on determining that a second receiver formatting interface is selected by the first output indicator, the controller performs the alignment adjustment and output of the first packet by the second receiver formatting interface.
    Type: Application
    Filed: May 15, 2017
    Publication date: March 29, 2018
    Inventors: Jeffrey C. Hanscom, Eric N. Lais, John M. Pritz
  • Publication number: 20180018297
    Abstract: Embodiments include methods, systems, and computer program products for performing synchronous data I/O. Aspects include a processor of computer system sending a store block to request data from a device through a PCIe connection, requested data having a predetermined number of data blocks, and the processor executing a data transaction loop to retrieve requested data. Executing the data transaction loop may include writing to a table prefetch trigger register on host bridge to queue up speculative prefetches in ETU for each data block. The host bridge may perform a first speculative prefetch to install a device table entry in a device table cache. The processor may further perform a second speculative prefetch to install an address translation in an address translation cache. The host bridge processes the data block received through direct memory access over the PCIe connection using the prefetched device table entry and address translation.
    Type: Application
    Filed: July 13, 2016
    Publication date: January 18, 2018
    Inventors: David F. Craddock, Matthias Klein, Eric N. Lais
  • Publication number: 20180004664
    Abstract: A synchronous input/output (I/O) computing system includes a processor and a memory unit that stores program instructions. The system purges one or more address translation entries in response to the processor executing the program instructions to issue, via an operating system running on the synchronous I/O computing system, a synchronous I/O command indicating a request to perform a transaction. The program instructions further command the operating system to select a device table entry from a device table, load the entry into the DTC, request required address translation entries, install the required address translation entries in the address translation cache, and transfer data packets corresponding to the transaction. The program instructions further command the operating system to automatically purge the address translation cache entries associated with a transaction in response to detect that the transaction is completed.
    Type: Application
    Filed: June 29, 2016
    Publication date: January 4, 2018
    Inventors: David F. Craddock, Matthias Klein, Eric N. Lais
  • Publication number: 20170371816
    Abstract: A computing system includes a processor and a memory unit that stores program instructions. The system purges an entry from an address translation cache in response to the processor executing the program instructions to perform issuing, via an operating system running on the computing system, a command indicating a request to perform an I/O transaction requiring a translation entry. A host bridge monitors a total data length of the address translation entry to be transferred during the I/O transaction. An address translation entry is selected from an address translation table, loaded into the address translation cache, and data corresponding to the I/O transaction is transferred using the selected address translation entry. The host bridge automatically purges the selected address translation entry from the address translation cache in response to determining the transferred amount of data matches the total data length for the address translation entry.
    Type: Application
    Filed: June 27, 2016
    Publication date: December 28, 2017
    Inventors: Matthias Klein, Eric N. Lais, Darwin W. Norton, JR.
  • Publication number: 20170371813
    Abstract: A computer-implemented method for synchronous input/output (I/O) cache line padding is described. The cache line padding occurs between a server having a processor executing an operating system and a recipient control unit. The method can include receiving, via the processor at the recipient control unit, a partial line direct memory access (DMA) write request; fetching, via the processor, a device table entry (DTE) associated with the partial line DMA write request; determining, via the processor, a cache line size for a synchronous input/output (I/O) cache line; and writing a full cache line DMA write request by padding, via the processor, the partial line DMA write request with a padded portion, where the padded portion is based on the cache line size.
    Type: Application
    Filed: June 23, 2016
    Publication date: December 28, 2017
    Inventors: Scott A. Brewer, David F. Craddock, Matthew J. Kalos, Matthias Klein, Eric N. Lais
  • Publication number: 20170371828
    Abstract: A computer-implemented method for computer-implemented method for communicating completion of synchronous input/output (I/O) commands between a processor executing an operating system and a recipient control unit is described. The method may include issuing, by a processor, a Synchronous I/O command to the recipient control unit; receiving, with the processor, a DMA read request from the recipient control unit; converting, with the processor, the DMA read response to write a data record into memory of the recipient control unit; issuing the DMA read request to the recipient control unit, wherein the DMA read request comprises an echo read portion comprising at least one byte of information at the end of the data record written; receiving, by the processor, a DMA write confirmation comprising the echo read portion of the record; and writing the echo read portion to a status area.
    Type: Application
    Filed: June 23, 2016
    Publication date: December 28, 2017
    Inventors: Scott A. Brewer, David F. Craddock, Matthew J. Kalos, Matthias Klein, Eric N. Lais
  • Publication number: 20170322894
    Abstract: A synchronous input/output (I/O) computing system includes a processor and a memory unit that stores program instructions. The system is configured to purge a device table cache (DTC) in response to the processor executing the program instructions. An operating system runs on the synchronous I/O computing system and issues a synchronous I/O command indicating a request to perform a device table entry transaction that has a total data length to be transferred. A device table entry is selected from a device table, loaded into the DTC, and data packets corresponding to the device table entry transaction are transferred using the selected device table entry. A host bridge processor monitors the data packets transferred using the selected table entry, and automatically purges the selected device table entry from the DTC in response to determining the transferred data packets match the total data length.
    Type: Application
    Filed: May 9, 2016
    Publication date: November 9, 2017
    Inventors: David F. Craddock, Matthias Klein, Eric N. Lais
  • Publication number: 20170317691
    Abstract: Examples of techniques for hardware assisted data protection are disclosed. In one example implementation according to aspects of the present disclosure, a method may include receiving a read data record comprising at least one memory write, the read data record having an associated cyclic redundancy check (CRC). The method may further include calculating, by a hardware module, an expected CRC for the read data record. Additionally, the method may include comparing the expected CRC to a known CRC stored in a known CRC data store. Finally, the method may include authenticating the read data record when the expected CRC matches a corresponding known CRC.
    Type: Application
    Filed: April 29, 2016
    Publication date: November 2, 2017
    Inventors: David F. Craddock, Matthias Klein, Eric N. Lais, Peter G. Sutton, Harry M. Yudenfriend
  • Publication number: 20170315863
    Abstract: Examples of techniques for hardware assisted data protection are disclosed. In one example implementation according to aspects of the present disclosure, a method may include receiving a read data record comprising at least one memory write, the read data record having an associated cyclic redundancy check (CRC). The method may further include calculating, by a hardware module, an expected CRC for the read data record. Additionally, the method may include comparing the expected CRC to a known CRC stored in a known CRC data store. Finally, the method may include authenticating the read data record when the expected CRC matches a corresponding known CRC.
    Type: Application
    Filed: May 5, 2016
    Publication date: November 2, 2017
    Inventors: David F. Craddock, Matthias Klein, Eric N. Lais, Peter G. Sutton, Harry M. Yudenfriend
  • Publication number: 20170315864
    Abstract: Examples of techniques for hardware assisted data protection are disclosed. In one example implementation according to aspects of the present disclosure, a method may include receiving a read data record comprising at least one memory write, the read data record having an associated cyclic redundancy check (CRC). The method may further include calculating, by a hardware module, an expected CRC for the read data record. Additionally, the method may include comparing the expected CRC to a known CRC stored in a known CRC data store. Finally, the method may include authenticating the read data record when the expected CRC matches a corresponding known CRC.
    Type: Application
    Filed: May 5, 2016
    Publication date: November 2, 2017
    Inventors: David F. Craddock, Matthias Klein, Eric N. Lais, Peter G. Sutton, Harry M. Yudenfriend