Patents by Inventor N. Lay

N. Lay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110320643
    Abstract: A measurement facility is provided for capturing and presenting fine-grained usage information for adapter functions in an input/output subsystem. Adapter specific input/output traffic is tracked on a per function basis and the results are dynamically presented to the user. This information is useful for performance tuning, load balancing and usage based charging, as examples.
    Type: Application
    Filed: June 23, 2010
    Publication date: December 29, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Frank W. Brice, JR., David Craddock, Beth A. Glendening, Thomas A. Gregg, Eric N. Lais, Peter K. Szwed, Stephen G. Wilkins
  • Patent number: 7669010
    Abstract: A system, method and article of manufacture for reducing latencies associated with cache coherence directory misses on external caches in a shared distributed memory data processing system. A cache coherence directory is evaluated for possible prefetching of a directory entry into a directory cache. A prefetch miss indicator is set if the prefetch evaluated results in a directory miss. The prefetch miss indicator is consulted during subsequent processing of a memory block request corresponding to the directory entry. An accelerated snoop response action is taken if the prefetch miss indicator is set. The latency of a second lookup into the cache coherence directory, which would otherwise be required, is thereby avoided.
    Type: Grant
    Filed: April 18, 2008
    Date of Patent: February 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Eric N. Lais, Donald R. DeSota, Rob Joersz
  • Publication number: 20080195820
    Abstract: A system, method and article of manufacture for reducing latencies associated with cache coherence directory misses on external caches in a shared distributed memory data processing system. A cache coherence directory is evaluated for possible prefetching of a directory entry into a directory cache. A prefetch miss indicator is set if the prefetch evaluated results in a directory miss. The prefetch miss indicator is consulted during subsequent processing of a memory block request corresponding to the directory entry. An accelerated snoop response action is taken if the prefetch miss indicator is set. The latency of a second lookup into the cache coherence directory, which would otherwise be required, is thereby avoided.
    Type: Application
    Filed: April 18, 2008
    Publication date: August 14, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Eric N. Lais, Donald R. DeSota, Rob Joersz
  • Patent number: 7395375
    Abstract: A system, method and article of manufacture for reducing latencies associated with cache coherence directory misses on external caches in a shared distributed memory data processing system. A cache coherence directory is evaluated for possible prefetching of a directory entry into a directory cache. A prefetch miss indicator is set if the prefetch evaluation results in a directory miss. The prefetch miss indicator is consulted during subsequent processing of a memory block request corresponding to the directory entry. An accelerated snoop response action is taken if the prefetch miss indicator is set. The latency of a second lookup into the cache coherence directory, which would otherwise be required, is thereby avoided.
    Type: Grant
    Filed: November 8, 2004
    Date of Patent: July 1, 2008
    Assignee: International Business Machines Corporation
    Inventors: Eric N. Lais, Donald R. DeSota, Rob Joersz
  • Patent number: 6996665
    Abstract: A hazard queue for a pipeline, such as a multiple-stage pipeline for transaction conversion, is disclosed. A transaction in the pipeline is determined to represent a hazard relative to another transaction, such as by evaluating the transaction against a hazard content-addressable memory (CAM). The hazard CAM can enforce various hazard rules, such as considering a transaction as active if it is referencing a memory line and is currently being processed within the pipeline, and ensuring that only one active transaction with a given coherent memory line is in the pipeline at a single time. In response to determining that a transaction is a hazard, the transaction is routed to a hazard queue, such as at the end of the pipeline. Once the hazard is released, the transaction re-enters the pipeline.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: February 7, 2006
    Assignee: International Business Machines Corporation
    Inventors: Donald R. DeSota, Bruce M. Gilbert, Robert Joersz, Eric N. Lais, Maged M. Michael
  • Publication number: 20050261799
    Abstract: Method and apparatus to detect a change in a work tool with an engaging portion. A control system senses a change in the relationship between the engaging portion of the work tool and at least one of the work tool and another engaging portion of the work tool. If the change is greater than a predetermined value, the control system produces an error signal.
    Type: Application
    Filed: May 19, 2004
    Publication date: November 24, 2005
    Inventors: Ronald Groth, Carl Kemner, N. Lay
  • Patent number: 6922755
    Abstract: A multinode, multiprocessor computer system with distributed shared memory has reduced hardware and improved performance by providing a directory free environment. Without a directory, nodes do not track where cache lines are stored in caches on other nodes. In two-node systems, cache lines are implied to be either on the local node or cached at the remote node or both. Thus, if a local node has a cache miss it is implied that the other node in the system has the cache line. In another aspect, the system allows for “silent rollouts.” In prior distributed memory multiprocessor systems, when a remote node has capacity limitations, it must overwrite (i.e., rollout) a cache line and report to the home node that the rollout occurred. However, the described system allows the remote node to rollout a cache line without reporting to the home node that the rollout occurred. Such a silent rollout can create timing problems because the home node still believes the remote node has a shared copy of the cache line.
    Type: Grant
    Filed: February 18, 2000
    Date of Patent: July 26, 2005
    Assignee: International Business Machines Corporation
    Inventors: Robert J. Safranek, Eric N. Lais
  • Publication number: 20040128461
    Abstract: A hazard queue for a pipeline, such as a multiple-stage pipeline for transaction conversion, is disclosed. A transaction in the pipeline is determined to represent a hazard relative to another transaction, such as by evaluating the transaction against a hazard content-addressable memory (CAM). The hazard CAM can enforce various hazard rules, such as considering a transaction as active if it is referencing a memory line and is currently being processed within the pipeline, and ensuring that only one active transaction with a given coherent memory line is in the pipeline at a single time. In response to determining that a transaction is a hazard, the transaction is routed to a hazard queue, such as at the end of the pipeline. Once the hazard is released, the transaction re-enters the pipeline.
    Type: Application
    Filed: December 30, 2002
    Publication date: July 1, 2004
    Applicant: International Business Machines Corporation
    Inventors: Donald R. DeSota, Bruce M. Gilbert, Robert Joersz, Eric N. Lais, Maged M. Michael
  • Publication number: 20030052711
    Abstract: A reconfigurable chip includes a despreader/correlator function back in order to better implement communication protocols which require despreading and/or correlation. These despreader/correlation functional blocks are used in addition to reconfigurable functional blocks having arithmetic logic units. The functions of the despreader/correlator functional blocks are preferably controlled by instructions from a local instruction memory.
    Type: Application
    Filed: September 19, 2001
    Publication date: March 20, 2003
    Inventors: Bradley L. Taylor, Gary N. Lai
  • Publication number: 20030055861
    Abstract: A multiplication block for a reconfigurable chip includes multiple multiplication units and a group of the selectable adder units operably interconnectable with the multiplication units. The adder units can be selectively connected for different configurations. The multiplication block is preferably controlled by an instruction which can put the multiplication block into different configurations.
    Type: Application
    Filed: September 18, 2001
    Publication date: March 20, 2003
    Inventors: Gary N. Lai, Joshua James Lindner
  • Patent number: 6483343
    Abstract: A plurality of configurable computational units are embedded in a programmable device, such as a field programmable gate array. Each configurable computational unit includes an adder circuit that is switchably coupled to a multiplier circuit and an accumulator circuit. The configurable computational unit may be configured permanently or on-the-fly to perform desired arithmetic type functions efficiently and effectively. For example, the computational unit may be configured for digital signal processing functions, filtering functions, and algorithm functions. The computational units may be cascaded by programmably connecting the computational units together, e.g., through the routing resources of the programmable device.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: November 19, 2002
    Assignee: QuickLogic Corporation
    Inventors: Brian C. Faith, Thomas Oelsner, Gary N. Lai
  • Publication number: 20020038414
    Abstract: A reconfigurable logic system using reconfigurable functional units of the type having arithmetic logic units are associated with address generating memory units. The address generating memory units having address generators that can construct addresses for memory in the address generator memory units. This frees the reconfigurable functional unit from the need to construct a sequence of addresses for the memory unit.
    Type: Application
    Filed: September 28, 2001
    Publication date: March 28, 2002
    Inventors: Bradley L. Taylor, Gary N. Lai