Abstract: An average power tracking (APT) power management circuit is provided. The APT power management circuit is configured to generate a first APT voltage(s) for a first power amplifier(s) and a second APT voltage(s) for a second power amplifier(s). The APT power management circuit further includes a pair of switcher circuits that can generate a pair of reference voltages. Depending on various operating scenarios of the APT power management circuit, it is possible to selectively output any of the reference voltages as any one or more of the first APT voltage(s) and the second APT voltage(s). As such, it is possible to flexibly configure the APT power management circuit to support the various operating scenarios based on a minimum possible number of the switcher circuits, thus helping to reduce footprint and cost of the APT power management circuit.

Abstract: An envelope tracking (ET) circuit and related power amplifier apparatus is provided. An ET power amplifier apparatus includes an ET circuit and a number of amplifier circuits. The ET circuit is configured to provide a number of ET modulated voltages to the amplifier circuits for amplifying concurrently a number of radio frequency (RF) signals. The ET circuit includes a target voltage circuit for generating a number of ET target voltages adapted to respective power levels of the RF signals and/or respective impedances seen by the amplifier circuits, a supply voltage circuit for generating a number of constant voltages, and an ET voltage circuit for generating the ET modulated voltages based on the ET target voltages and a selected one of the constant voltages. By employing a single ET circuit, it may be possible to reduce the footprint and improve heat dissipation of the ET power amplifier apparatus.

Abstract: An acoustic filter circuit for noise suppression outside resonance frequency is provided. The acoustic filter circuit includes a first filter branch and a second filter branch. The first filter branch and the second filter branch are both configured to resonate at a resonance frequency to pass a radio frequency (RF) signal, but in opposite phases. The acoustic filter circuit also includes a shunt circuit coupled between the first filter branch and the second filter branch. As discussed in various embodiments in the detailed description, the shunt circuit can be configured to protect the RF signal located inside the resonance frequency and suppress noises located outside the resonance frequency. As such, the acoustic filter circuit can provide improved noise rejection and reduce insertion loss.

Abstract: A switch controller for charge pump tracker circuitry is disclosed. The switch controller includes first monitoring circuitry configured to monitor a first voltage across a first flying capacitor during a first discharging phase. A second monitoring circuitry is configured to monitor a second voltage across a second flying capacitor during a second discharging phase. Further included is boost logic circuitry in communication with the first monitoring circuitry and the second monitoring circuitry, wherein the boost logic circuitry is configured in response to control a first switch network coupled to the first flying capacitor and a second switch network coupled to the second flying capacitor so that the first discharging phase and the second discharging phase alternate in an interleaved mode, and so that the first discharging phase and the second discharging phase are in phase during a parallel boost mode.

Abstract: A wide-bandwidth resonant circuit is provided. In an embodiment disclosed herein, the wide-bandwidth resonant circuit includes a positive resonant circuit coupled in parallel to a negative resonant circuit. The positive resonant circuit and the negative resonant circuit can be configured to collectively exhibit certain impedance characteristics across a wide bandwidth. As a result, it is possible to utilize the wide-bandwidth resonant circuit to support a variety of wide-bandwidth applications, such as in a wide-bandwidth signal filter circuit.

Abstract: The present disclosure relates to a switch system that provides a control method for switches based on dual-phase materials. The disclosed switch system includes a heat resistor, a power management (PM) unit configured to provide a control voltage at a voltage port coupled to the heat resistor, and a phase-change-based switch. Herein, the heat resistor is underneath the phase-change-based switch, and configured to generate heat energy from the control voltage and provide the heat energy to the phase-change-based switch. The phase-change-based switch is capable of being switched on and off by switching between a crystalline phase and an amorphous phase based on the heat energy provided by the heat resistor. The control voltage provided by the PM unit contains waveform information of target heat energy required for switching on and off the phase-change-based switch.

Abstract: An average power tracking (APT) power management circuit is provided. The APT power management circuit is configured to generate a first APT voltage(s) for a first power amplifier(s) and a second APT voltage(s) for a second power amplifier(s). The APT power management circuit further includes a pair of switcher circuits that can generate a pair of reference voltages. Depending on various operating scenarios of the APT power management circuit, it is possible to selectively output any of the reference voltages as any one or more of the first APT voltage(s) and the second APT voltage(s). As such, it is possible to flexibly configure the APT power management circuit to support the various operating scenarios based on a minimum possible number of the switcher circuits, thus helping to reduce footprint and cost of the APT power management circuit.

Abstract: An inverted group delay circuit is provided. The inverted group delay circuit can offset a group delay between a pair of signals. In a non-limiting example, the inverted group delay circuit can be configured to offset a group delay (e.g., negative group delay) between a time-variant voltage and a time-variant envelope of an analog signal. More specifically, the inverted group delay circuit can output an inverted time-variant voltage having an opposing phase and time-adjusted relative to the time-variant voltage to thereby offset the group delay between the time-variant voltage and the time-variant envelope. As such, the inverted group delay circuit can be provided in a power management integrated circuit (PMIC) to improve timing alignment between a time-variant voltage(s) and a time-variant analog signal(s) at a power amplifier(s), thus helping to reduce potential amplitude distortion when the analog signal(s) is amplified by the power amplifier(s).

Abstract: An average power tracking (APT) power management integrated circuit (PMIC) is provided. The APT PMIC is configured to generate an APT voltage to a power amplifier for amplifying a high modulation bandwidth (e.g., ?200 MHz) radio frequency (RF) signal. The APT PMIC includes a voltage amplifier configured to generate an initial APT voltage and an offset capacitor configured to raise the initial APT voltage by a modulated offset voltage. The APT PMIC can be configured to modulate the initial APT voltage and the modulated offset voltage concurrently based on a time-variant APT target voltage. As a result, the APT PMIC can adapt the APT voltage very quickly between different voltage levels, thus making it possible to amplify a high modulation bandwidth radio frequency (RF) signal for transmission in a fifth-generation (5G) communication system.

Abstract: A wide bandwidth power amplifier apparatus is provided. The wide bandwidth power amplifier apparatus includes a power amplifier circuit, a primary switcher circuit, a voltage circuit(s), and an auxiliary switcher circuit(s). The power amplifier circuit is configured to amplify a radio frequency (RF) signal based on a modulated voltage and a modulated current. The voltage circuit is configured to generate the modulated voltage and a respective part of the modulated current. The primary switcher circuit and the auxiliary switcher circuit are each configured to also generate a respective part of the modulated current. The auxiliary switcher circuit only generates the respective part of the modulated current when a bandwidth of the modulated voltage exceeds a bandwidth threshold. As such, it is possible to prevent the voltage circuit from having to source additional current when the modulated voltage exceeds the bandwidth threshold, thus helping to improve efficiency of the voltage circuit.

Abstract: A multi-transmission power management circuit is provided. In embodiments disclosed herein, the multi-transmission power management circuit includes multiple quadrature power amplifier circuits each configured to concurrently generate multiple amplified radio frequency (RF) signals based on a respective modulated voltage(s). The multi-transmission power management circuit also includes an envelope tracking (ET) integrated circuit (ETIC) configured to concurrently generate multiple modulated voltages. A control circuit is configured to determine one or more of the multiple quadrature power amplifier circuits that are involved in a multi-transmission scheme. Accordingly, the control circuit can cause the ETIC to provide one or more of the multiple modulated voltages to each of the quadrature power amplifier circuits involved in the multi-transmission scheme. In this regard, the multi-transmission power management circuit can be flexibly configured to support different multi-transmission schemes.

Abstract: A power amplifier system is disclosed having a first amplifier with a high-power input and a high-power output. A second amplifier has a low-power input and a low-power output. A reconfigurable mode switch network has a first series switch branch coupled between the high-power output and an RF output, a first shunt branch is coupled between the RF output and a fixed voltage node, and a second series switch branch is coupled between the low-power output and a shared node of the first shunt branch. The shared node separates the first shunt branch into a first shared section that is between the RF output and the shared node and a second shared section that is between the shared node and the fixed voltage node.

Abstract: A power amplifier system is disclosed with a carrier amplifier having a carrier bias input and a carrier supply node and a peaking amplifier having a peaking bias input and a peaking supply node. Also included is an envelope tracking power supply having a modulated voltage supply output coupled to the peaking supply node. Further included is a peaking bias controller having a peaking bias control input coupled to the peaking supply node and a peaking bias control output coupled to the peaking bias input, wherein the peaking bias controller is configured to generate in response to a modulated peaking supply voltage generated by the envelope tracking power supply at the peaking supply node a modulated peaking bias signal that controls bias of the peaking amplifier.

Abstract: A virtual radio frequency (VRF) equalizer for an envelope tracking integrated circuit (ETIC) is disclosed. In one aspect, an ETIC provides envelope tracking (ET) for a barely Doherty (BD) power amplifier stage. The VRF equalizer includes circuitry that provides ripple cancelation that is caused by load modulation of the BD power amplifier stage. Additional circuitry is included to compensate for an amplifier within the ETIC. By canceling the ripple within the ETIC, the overall performance and efficiency of the BD power amplifier stage is improved, resulting in better performance of a transmitter in a wireless communication device.

Abstract: Disclosed is envelope tracking circuitry having an envelope tracking integrated circuit (ETIC) coupled to a power supply to provide an envelope tracked power signal to a power amplifier (PA) with a filter equalizer configured to inject an error-correcting signal into the ETIC in response to equalizer settings. Further included is PA resistance estimator circuitry having a first peak detector circuit configured to capture within a window first peaks associated with a sense current generated by the ETIC, a second peak detector circuit configured to capture within the window second peaks associated with a scaled supply voltage corresponding to the envelope tracked power signal, comparator circuitry configured to receive the first peaks and receive the second peaks and generate an estimation of PA resistance, and an equalizer settings correction circuit configured to receive the estimation of PA resistance and update the equalizer settings in response to the estimation of PA resistance.

Abstract: Voltage ripple reduction in a power management circuit is disclosed. The power management circuit includes a power amplifier circuit configured to amplify a radio frequency (RF) signal based on a modulated voltage and an envelope tracking integrated circuit (ETIC) configured to provide the modulated voltage to the power amplifier circuit via a conductive path. Notably, an output impedance presenting at an input of the power amplifier circuit can interact with a modulated load current in the power amplifier circuit to create a voltage ripple in the modulated voltage to potentially cause an undesirable error in the RF signal. Herein, the ETIC is configured to modify the modulated voltage based on feedback of the voltage ripple in the modulated voltage. As such, it is possible to reduce the output impedance at the input of the power amplifier circuit to thereby reduce the voltage ripple in the modulated voltage.

Abstract: Slave-initiated communications over a single-wire bus are described in the present disclosure. In contrast to a conventional single-wire bus apparatus wherein communications over the single-wire bus are always initiated by a master circuit, a single-wire bus apparatus disclosed herein allows a slave circuit(s) to initiate communications over the single-wire bus. More specifically, multiple slave circuits can concurrently contend for access to the single-wire bus via current mode signaling (CMS). In response to the CMS asserted by the multiple slave circuits, a master circuit provides a number of pulse-width modulation (PWM) symbols over the single-wire bus to indicate which of the multiple slave circuits is granted access to the single-wire bus. By supporting slave-initiated communications over the single-wire bus, it is possible to improve efficiency, cost, and power consumption in an electronic device (e.g., smartphone) wherein the single-wire bus apparatus is deployed.

Abstract: A multi-protocol bus circuit is provided. The multi-protocol bus circuit includes multiple master circuits each configured to communicate a respective master bus command(s) via a respective one of multiple master buses based on a respective one of multiple master bus protocols, and a slave circuit(s) configured to communicate a slave bus command(s) via a slave bus based on a slave bus protocol that is different from any of the master bus protocols. To enable bidirectional bus communications between the master circuits and the slave circuit(s), the multi-protocol bus circuit further includes a multi-protocol bridge circuit configured to perform a bidirectional conversion between the slave bus protocol and each of the master bus protocols. As a result, it is possible to support bidirectional bus communications based on heterogeneous bus protocols with minimal impact on cost and/or footprint.

Abstract: A fast-switching power management circuit operable to prolong battery life is provided. The power management circuit includes a voltage circuit that can generate an output voltage for amplifying an analog signal in a number of time intervals and a pair of hybrid circuits each causing the output voltage to change in any of the time intervals. A control circuit is configured to activate any one of the hybrid circuits during a preceding one of the time intervals to cause the output voltage to change in an immediately succeeding one of the time intervals. By starting the output voltage change earlier in the preceding time interval, it is possible to complete the output voltage change within a switching window in the succeeding time interval while concurrently reducing rush current associated with the output voltage change, thus helping to prolong battery life in a device employing the power management circuit.

Abstract: A multi-protocol bus circuit is provided. The multi-protocol bus circuit includes multiple master circuits each configured to communicate a respective master bus command(s) via a respective one of multiple master buses based on a respective one of multiple master bus protocols, and a slave circuit(s) configured to communicate a slave bus command(s) via a slave bus based on a slave bus protocol that is different from any of the master bus protocols. To enable bidirectional bus communications between the master circuits and the slave circuit(s), the multi-protocol bus circuit further includes a multi-protocol bridge circuit configured to perform a bidirectional conversion between the slave bus protocol and each of the master bus protocols. As a result, it is possible to support bidirectional bus communications based on heterogeneous bus protocols with minimal impact on cost and/or footprint.