Abstract: Some of the embodiments of the present disclosure provide a method comprising performing, by an iterative parser and classifier engine, a first parsing and classification cycle on a data packet, based at least in part on header information of the data packet; generating a first parsing and classification result based at least in part on performing the first parsing and classification cycle; and performing a second parsing and classification cycle on the data packet, based at least in part on header information of the data packet and the first parsing and classification result. Other embodiments are also described and claimed.

Abstract: An apparatus includes ports to transmit and receive packets, each packet being associated with one of a plurality of sessions, and a packet buffer to store the packets. A classifier identifies packets that include data representing a transmit window size for one of the sessions. A processor determines whether to reduce the transmit window size for the one of the sessions by comparing a size of the packet buffer to a sum of (i) the transmit window size for the one of the sessions and (ii) transmit window sizes for others of the sessions. The processor modifies the data representing the transmit window size for the one of the sessions to reduce the transmit window size for the one of the sessions before one or more of the ports transmits the packets comprising the data representing the transmit window size for the one of the sessions.

Abstract: A system and method of managing data packets for transmission in a virtual network are disclosed. In some implementations, a network switch may generally comprise a packet modifier that modifies a VLAN tag state of a packet to be egressed as a function of an egress interface and a VLAN-ID assignment. The modified VLAN tag state may include one or more VLAN tags that are in a different order, or that have a different content, in comparison to the VLAN tags of the packet at the time of ingress.

Abstract: A network device includes an alignment module to align payloads of received frames on memory boundaries in a buffer memory. The frames may be Ethernet frames which encapsulate IP (Internet Protocol) packets as payloads. The alignment module modifies the frame to shift the IP payload into a position in the memory regions such that the IP payload is aligned with the memory boundaries. The number x of non-data bits can be determined according to x=m*c+p, where m is the bit depth of memory regions, n is the length of a header, p is the non-zero remainder of the ratio n/m, and c is an integer.

Abstract: A network device comprises a data translator that receives a first data stream at a first data rate and that includes a data sampler that selects one of X data symbols that are received, wherein the one of the X data symbols includes (M+N) bits, and that outputs a second data stream at a second data rate and a data remover that removes N of the (M+N) bits and that outputs a third data stream including symbols with the M bits at a third data rate. A physical layer device receives the third data stream.

Abstract: A method, apparatus, and computer-readable media for a switch comprising a plurality of network ports and a central processing unit (CPU) interface comprises receiving, on one of the network ports, a packet comprising a source media access control (MAC) address; sending, to the CPU interface, a request to approve an association between the one of the network ports and the source MAC address when no request to approve the association between the one of the network ports and the source MAC address has been sent to the CPU interface; and sending, to the CPU interface, the request to approve the association between the one of the network ports and the source MAC address when an association between the source MAC address and a different one of the network ports has been approved.

Abstract: An apparatus having a corresponding method and computer program comprises a processor; a plurality of ports to transmit and receive packets of data, the plurality of ports comprising a processor port in communication with the processor, the packets comprising broadcast packets and multicast packets; a memory to store a table that associates the processor port with one or more Internet protocol (IP) addresses; and a forwarding engine to transfer the packets between the ports, to transfer each of the broadcast packets to the processor port only when the table associates a target IP address of the broadcast packet with the processor port, and to transfer each of the multicast packets to the processor port only when the table associates a target IP address of the multicast packet with the processor port.

Abstract: A network switch comprises a port that includes a redirect circuit and a loopback circuit that selectively redirects an egress frame to the redirect circuit when the port is non-operational. The redirect circuit replaces a destination port identifier associated with the egress frame to create a modified frame. The loopback circuit loops back the modified frame in an ingress direction. A transfer circuit transfers the modified frame to another port identified by the destination port identifier.

Abstract: The present disclosure includes systems and techniques relating to virtual Ethernet switches. In some implementations, a system includes two or more Ethernet switches. Two or more components are included in the system to open at least one tunnel, over a network, between the two or more Ethernet switches to connect the two or more Ethernet switches together. In addition, two or more components are included in the system to operate a protocol over the opened at least one tunnel to manage the two or more Ethernet switches as a single unit that shares at least one network feature among all of the two or more Ethernet switches.

Abstract: A stack unit for a stackable network switch, the stack unit having corresponding methods and computer programs, comprises a network port to exchange packets with a network; two stacking interfaces each to exchange the packets over a respective stacking link with another stack unit, wherein each stacking interface is assigned to the other stacking interface as an alternate stacking interface; and a forwarding engine to transfer the packets among the stacking interfaces and network port; wherein when one of the stacking links is down, the respective stacking interface toggles a loop flag in each packet received from the forwarding engine, and returns each received packet to the forwarding engine; and wherein the forwarding engine transfers each packet received from one of the stacking interfaces to the respective alternate stacking interface when the loop flag for the packet is set.

Abstract: Method and apparatus for modifying standard VLAN tags to perform network packet switching. The method includes receiving a data packet at a port of a network switch and determining whether the data packet has a virtual local area network (VLAN) tagged frame. If the received data packet has a VLAN tagged frame, then the method further includes modifying and encoding fixed portions of the VLAN tag frame with switching information. The switching information includes information for central management of data packet flow through the network switch.

Abstract: A double data rate SMII circuit comprises a transmit circuit, responsive to a clock signal, that samples serial transmit data on a clock rising edge to generate a first transmit serial stream. The transmit circuit, responsive to the clock signal, samples the serial transmit data on a clock falling edge to generate a second transmit serial stream. A receive circuit, responsive to the clock signal, generates a receive serial stream from two receive data streams. The receive serial stream having a first operating frequency, each of the two receive data streams having a second operating frequency. The first operating frequency is about twice the second operating frequency. A transmit port, corresponding to the transmit circuit, includes a single terminal to communicate the serial transmit data to the transmit circuit. A receive port, corresponding to the receive circuit, includes a single terminal to communicate the receive serial stream from the receive circuit.

Abstract: An apparatus having a corresponding method and computer program comprises network interfaces; a processor interface; a control circuit to remove the processor interface from associations between the interfaces and a domain; a classifier to assign codes to packets addressed to the processor interface, wherein the each code represents a protocol and comprises a flag; an allowance circuit to set the flag in the code for a packet when the packet comprises a protocol associated with the network interface that is the source of the packet, and to clear the flag otherwise; and an egress circuit to receive packets addressed to the processor interface, to drop the received packets having a code comprising a flag that is clear, and to transfer the received packets having a code comprising a flag that is set to the processor interface.

Abstract: A network switch includes a matching device that employs a first data structure to select one of N address groups including a first partial address of an IP packet. An action table selects one of a next hop location corresponding to a longest prefix match and a first matching operation for the IP packet based on the selected one of the N groups. When the first matching operation is selected, the matching device employs a second data structure to select one of M address groups including a second partial address of the IP packet. The action table selects one of a next hop location corresponding to a longest prefix match and a second matching operation for the IP packet based on the selected one of the M groups. A routing engine routes the IP packet based on the first and second next hop locations.

Abstract: A wireless network apparatus and corresponding method and computer program comprises a plurality of ports to transmit and receive data flows comprising packets of data; a memory to store a routing table; a forwarding engine to transfer the packets of data between the ports according to the routing table; and a processor to define a routing interface comprising a selected group of the ports, map a selected media access control (MAC) address to the routing interface, disable link aggregation between the ports in the routing interface, disable bridging between the ports in the routing interface, and modify the routing table to direct each of the data flows having the MAC address as a destination address to one of the ports in the routing interface.

Abstract: The invention features a method, apparatus, and computer program. The apparatus comprises a plurality of ports each adapted to receive Ethernet packets; and a data-link layer switch controller, when one of the Ethernet packets comprises an Internet protocol (IP) multicast packet comprising an IP multicast destination address and an IP source address, to select one or more of the ports based upon the IP multicast destination address and the IP source address; wherein the selected one or more ports transmit the Ethernet packet.

Abstract: A physical-layer device (PHY) having corresponding methods comprises: a data rate module to select a data rate divisor N, where N is at least one of a positive integer, or a real number greater than, or equal to, 1; and a PHY core comprising a PHY transmit module to transmit first signals a data rate of M/N Gbps, and a PHY receive module to receive second signals at the data rate of MIN Gbps; wherein the first and second signals conform to at least one of 1000BASE-T, wherein M=1, and 10GBASE-T, wherein M=10.

Abstract: A system and method of managing data packets for transmission in a virtual network are disclosed. In some implementations, a network switch may generally comprise a packet modifier that modifies a VLAN tag state of a packet to be egressed as a function of an egress interface and a VLAN-ID assignment. The modified VLAN tag state may include one or more VLAN tags that are in a different order, or that have a different content, in comparison to the VLAN tags of the packet at the time of ingress.

Abstract: A packet processor for a switch/router alters headers of packets and includes a plurality of ports Memory buffers a first portion of a first packet that is received by an incoming port. A control data processor receives a first control portion of the first packet from the incoming port and transmits the first control portion to one or more outgoing ports. A header altering device strips, modifies and encapsulates the first portion on egress from the packet processor based upon one or more protocol layering requirements of the one or more outgoing ports. The protocol layering requirements include bridged or tunneled Ethernet, unicast or multicast multi-protocol label switching (MPLS), and IPv4 and IPv6 routed.

Abstract: A network device that operates in first and second serial gigabit interface modes involving data speed translation comprising a medium access control (MAC) device that transmits idle order sets. A physical layer (PHY) device receives the idle order sets and that switches from the first serial gigabit interface mode to the second serial gigabit interface mode if a first predetermined number of consecutive idle order sets are equal to a first idle order set.