Abstract: A network device includes an alignment module to align payloads of received frames on memory boundaries in a buffer memory. The frames may be Ethernet frames which encapsulate IP (Internet Protocol) packets as payloads. The alignment module prefixes non-data bits to the frame header to shift the IP payload into a position in the memory regions such that the IP payload is aligned with the memory boundaries. The number x of non-data bits is determined according to x=m*c+p, where m is the bit depth of memory regions, n is the length of a header, p is the non-zero remainder of the ratio n/m, and c is an integer.

Abstract: A network device includes a media access control (MAC) device that transmits a first data stream at a first data rate that includes symbols having M bits. A translator converts the first data stream to a second data stream at a second data rate. The translator includes a data appender that appends N bits to the symbols in the first data stream to generate second symbols having M+N bits. A data duplicator duplicates the second symbols X times to produce the second data stream at the second data rate.

Abstract: A network switch comprises a plurality of ports that exchange frames of data with one or more network devices. A transfer circuit transfers the frames of the data between the ports. At least one of the ports includes a loopback circuit that sends to the transfer circuit each frame of the data received by the at least one of the ports from the transfer circuit when the one of the ports is not operational. A redirect circuit causes the transfer circuit to transfer each frame of the data received by the transfer circuit from the one of the ports to one or more predetermined others of the ports when the one of the ports is not operational.

Abstract: Apparatus having corresponding methods and computer programs comprise a first port comprising a first transmitter to transmit a first packet to a first network, wherein the first packet identifies a first maximum size; a first receiver to receive second packets from the first network, wherein each second packet has a first size less than, or equal to, the first maximum size; and a second port comprising a second transmitter to transmit third packets to a second network, wherein the second network has a second maximum size greater than the first maximum size, wherein each third packet has a second size that is less than, or equal to, the second maximum size, and wherein each third packet comprises one of the second packets and a tunneling protocol header having a size that is less than, or equal to, a difference between the first maximum size and the second maximum size.

Abstract: Apparatus having corresponding methods and computer programs comprise a first first-in first-out buffer (FIFO) to receive and store data from a media access controller (MAC); a physical-layer device (PHY) to transmit a signal representing the data; and a control circuit comprising a read circuit to transfer the data from the first FIFO to the PHY, and a transmit pause circuit to transmit a pause frame to the MAC when an amount of the data stored in the first FIFO exceeds a predetermined threshold.

Abstract: A network device includes an alignment module to align payloads of received frames on memory boundaries in a buffer memory. The frames may be Ethernet frames which encapsulate IP (Inernet Protocol) packets as payloads. The alignment module prefixes dummy bytes to the frame header to shift the IP payload into an aligned position in the memory regions of the memory.

Abstract: A search engine improves search speed and reduces required memory for a longest prefix matching (LPM) router that routes packets using IP addresses. The search engine includes a first bit vector with set bits corresponding to address ranges. A set bit counter counts the set bits in the bit vector based on a first portion of the address of the a first packet. A first next hop table contains first pointers for each of the set bits. One of the first pointers is selected based on a number of set bits counted by the set bit counter. For longer addresses, the addresses are split into address portions. The search engine includes a trie data structure that has n levels. The n levels of the trie data structure include nodes representing non-overlapping address space.

Abstract: An apparatus, and method and computer program thereof, comprises a plurality of ports each adapted to receive packets of data; a memory controller core adapted to generate one or more memory transactions for each of the packets of the data, wherein each memory transaction comprises a payload having a size of m bytes, and wherein the payloads contain the data; a memory comprising a plurality of memory banks adapted to store the data, wherein the memory can receive no more than n bytes of data in a single memory transaction; and a memory interface adapted to transmit the memory transactions to the memory; wherein m=kn and k is an integer.

Abstract: A network switch, method and computer program product. The network switch comprises a plurality of ports each adapted to exchange frames of data with one or more network devices; a transfer circuit adapted to transfer the frames of the data between the ports; and wherein at least one of the ports comprises a loopback circuit adapted to send to the transfer circuit, when the one of the ports is not operational, each frame of the data received by the one of the ports from the transfer circuit, and a redirect circuit adapted to cause the transfer circuit to transfer, to one or more predetermined others of the ports, when the one of the ports is not operational, each frame of the data received by the transfer circuit from the one of the ports.

Abstract: An SMII interface circuit to communicate data synchronous with a clock signal having a rising edge and a falling edge. The interface circuit includes a transmit circuit that is responsive to the clock signal to generate a first transmit serial stream and a second transmit serial stream. A receive circuit, responsive to the clock signal, to generate a receive serial stream from two receive data streams. The receive serial stream having a operating frequency that is about twice the operating frequency of each of the two receive data streams. Transmit and receive ports corresponding to the transmit and receive circuits each include a single pin to communicate the serial transmit data and the receive serial stream.