Abstract: A resource manager of a virtualized computing service indicates to a client that FPGA-enabled compute instances are supported at the service. From a set of virtualization hosts of the service, a particular host from which an FPGA is accessible is selected for the client based on an indication of computation objectives of the client. Configuration operations are performed to prepare the host for the application, and an FPGA-enabled compute instance is launched at the host for the client.

Abstract: Technologies are provided for dynamically changing a size of a cache region of a storage device. A storage device controller writes data to the cache region of the storage device using a particular storage format. The storage device controller then migrates the cached data to a storage region of the device, where the data is written using a different storage format. A dynamic cache manager monitors input and output activity for the storage device and dynamically adjusts a size of the cache region to adapt to changes in the input and/or output activity. The dynamic cache manager can also adjust a size of the storage region. The storage device controller can automatically detect that the storage device has dynamic cache support and configure the storage device by creating the cache region and the storage region on the device.

Abstract: Methods and apparatus are disclosed for programming reconfigurable logic devices such as FPGAs in a networked server environment. In one example, a system hosting a network service providing field programmable gate array (FPGA) services includes a network service provider configured to receive a request to implement application logic in a plurality of FPGAs, allocate a computing instance comprising the FPGAs in responses to receiving the request, produce configuration information for programming the FPGAs, and send the configuration information to an allocated computing instance. The system further includes a computing host that is allocated by the network service provider as a computing instance which includes memory, processors configured to execute computer-executable instructions stored in the memory, and the programmed FPGAs.

Abstract: Technologies are provided for retrieving service level indicators (SLIs) for storage devices, prioritizing data access using the SLIs, and scheduling storage device maintenance based on the SLIs. A host computer can retrieve an SLI for a storage device and determine, using the SLI, whether the storage device is performing service and maintenance operations and/or whether the storage device is in need of performing service and maintenance operations. The host computer can retrieve SLIs for multiple storage devices storing data redundantly and prioritize using the storage devices to access the data based on the SLIs. If the host computer determines that a storage device is in need of maintenance, based on its SLI, the host computer can schedule the storage device for maintenance and divert data access requests to other storage devices until the maintenance is complete.

Abstract: A multi-tenant environment is described with configurable hardware logic (e.g., a Field Programmable Gate Array (FPGA)) positioned on a host server computer. For communicating with the configurable hardware logic, an intermediate host integrated circuit (IC) is positioned between the configurable hardware logic and virtual machines executing on the host server computer. The host IC can include management functionality and mapping functionality to map requests between the configurable hardware logic and the virtual machines. Shared peripherals can be located either on the host IC or the configurable hardware logic. The host IC can apportion resources amongst the different configurable hardware logics to ensure that no one customer can over consume resources.

Abstract: A resource request is received by a network device from a virtual machine running on a host. The resource request includes a requested resource size. The network device allocates resources of the network device in response to the resource request. A resource response is sent by the network device to the virtual machine that generated the resource request. The resource response includes a location of the allocated resource.

Abstract: Disclosed herein are techniques for preventing or minimizing completion timeout errors on a computer device. An apparatus include a processing logic circuit and a timeout logic. The timeout logic is configured to: generate a timeout event based on a transaction not completed by the processing logic circuit within a timeout period; determine a number of the timeout events generated during a monitoring period; and responsive to determining that the number equals to or exceeds a threshold, reduce the timeout period.

Abstract: Provided are systems and methods for enabling peer-to-peer communications between peripheral devices. In various implementations, a computing system can include a PCI switch device. The first PCI switch device can include a first port and be communicatively coupled to a first root complex port. The first PCI switch device can have access to a first PCI endpoint address range. The computing system can further include a second PCI switch device. The second PCI switch device can include a second port, connected to the first port. The second PCI switch device can be communicatively coupled to a second root complex port that is different from the first root complex port. The second PCI switch device can receive a transaction addressed to the first PCI endpoint address range, and identify the transaction as associated with the second port. The second PCI switch device can subsequently transmit the transaction using the second port.

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

Abstract: Disclosed are techniques regarding aspects of selectively enabling or disabling interconnects between peripheral processors. The peripheral processors may be included within a compute service provider and may be accessible via virtual machines within guest domains implemented within the compute service provider. The interconnects can be enabled or disabled depending upon whether they traverse domains of the compute service provider.

Abstract: Apparatus and methods are disclosed herein for remote, direct memory access (RDMA) technology that enables direct memory access from one host computer memory to another host computer memory over a physical or virtual computer network according to a number of different RDMA protocols. In one example, a method includes receiving remote direct memory access (RDMA) packets via a network adapter, deriving a protocol index identifying an RDMA protocol used to encode data for an RDMA transaction associated with the RDMA packets, applying the protocol index to a generate RDMA commands from header information in at least one of the received RDMA packets, and performing an RDMA operation using the RDMA commands.

Abstract: Disclosed herein is an apparatus configured to log transactions of a translation lookaside buffer (TLB) into a software-accessible buffer. The apparatus includes a memory management unit (MMU) configured to translate a logical memory address to a physical memory address for accessing a physical memory. The apparatus also includes a TLB configured to store a plurality of entries, where each entry includes a logical memory page address and an associated physical memory page address. The apparatus further includes a software-accessible buffer and a TLB event logging circuit configured to detect an event associated with an entry of the TLB and store information regarding the detected event in the software-accessible buffer.

Abstract: Disclosed are techniques regarding aspects of implementing client configurable logic within a computer system. The computer system can be a cloud infrastructure. The techniques can include providing an identifier in response to configuring client configurable logic within the computer system.

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

Abstract: Disclosed are techniques regarding aspects of implementing client configurable logic within a computer system. The computer system can be a cloud infrastructure. The techniques can include associating clock information with the client configurable logic for various purposes.

Abstract: A packet processing technique can include selecting a protocol field from the packet, and performing a comparison of the selected protocol field with comparison data in a compare logic array to output a protocol index. The protocol index can be used as an address to read parsing commands from a parse control table, and a parse result can be generated based on executing the parsing commands on the packet. The parse results are used to derive a parse result vector, which can be used by a forwarding engine to forward the packet.

Abstract: In various implementations, provided are techniques for verifying the accuracy of the network time maintained by a client device. In various implementations, a server can be configured to obtain network time information from a network. A particular client device can also obtain the network time information, and use the network time information to compute a network time for applications executing on the network device. The client device can periodically transmit the network time information to the mirror server. When the mirror server receives the time synchronization information from a client device, the mirror server can compare the client device's network time information to the network time information captured by the mirror server. In this way, the mirror server can verify the client device's time accuracy. The mirror server and/or the client device can subsequently perform a corrective action when the client device's time is not accurate.

Abstract: Provided are systems and methods for connection establishment over a network that does not require a user application to establish an explicit connection with a target application. In some implementations, provided is an apparatus configured to communicate with a network and a host device. The apparatus may receive a message and destination information associated with the message from the host device. The apparatus may further determine, using the destination information, a transport context from a plurality of transport contexts. The transport context may include a state of a connection with a destination on the network. The destination on the network may be associated with the destination information.

Abstract: A data or packet processing device such as a network interface controller may include cache control logic that is configured to obtain a set of memory descriptors associated with a queue from the memory. The set of descriptors can be stored in the cache. When a request for processing a data packet associated with the queue is received, the cache control logic can determine that the cache is storing memory descriptors for processing the data packet, and provide the memory descriptors used for processing the packet.

Abstract: Disclosed herein are techniques for maintaining a secure environment on a server. In one embodiment, the server includes a baseboard management controller (BMC), a first Ethernet port coupled with an adapter device network comprising a plurality of adapter devices, and a master adapter device including a second Ethernet port and a network switch, the network switch being controllable to be selectively coupled with at least one of the BMC, the first Ethernet port, or the second Ethernet port. The master adapter device may receive a network packet from at least one of: the first Ethernet port, the second Ethernet port, or the BMC, and determine, based on a forwarding policy, whether to forward the network packet. Based on a determination to forward the network packet, the master adapter device may determine a destination, and control the network switch to transmit the network packet to the destination.