Abstract: A storage system includes: a memory for caching of data according to input and output to a storage device; and a CPU connected to the memory. The memory includes: a DRAM high in access performance; and an SCM identical in a unit of access to the DRAM, the SCM being lower in access performance than the DRAM. The CPU determines whether to perform caching to the DRAM or the SCM, based on the data according to input and output to the storage device, and caches the data into the DRAM or the SCM, based on the determination.

Abstract: A storage device provides a logical space based on a storage medium that is configured by a plurality of logical areas to the higher-level apparatus, and a base data range exists in the storage medium for each logical area. The storage device reads the base data from the base data range that is corresponded to a write destination logical area to which the write destination logical address belongs, and creates difference data that is an exclusive OR of first data that is the base data and second data that is any one of data based on write data and the write data. The storage device creates compressed difference data by compressing the difference data, writes the compressed difference data to the storage medium, and associates a difference data range that is a range in which the compressed difference data has been written with the write destination logical area.

Abstract: A storage apparatus includes: a flash memory that provides a storage area; a controller that controls writing and reading of data to and from the storage area; and a buffer memory that temporarily stores data to be written in the storage area, in which the controller selects one compression method from a first reversible compression method and a second reversible compression method based on access performance to the flash memory, and determines to compress data based on the selected one compression method and to write the compressed data to the storage area, and the first reversible compression method has a lower compression ratio and a slower compression speed than the second reversible compression method.

Abstract: In a storage apparatus including a storage medium including a plurality of pages as a unit of reading and writing data, a first data block including a data block received from a higher-level device is generated, a second data block of a predetermined size including one or more undivided first data blocks is generated, a third data block in which a correction code is added to the second data block is generated, the third data block is stored in a page buffer, and one or more of the third data blocks stored in the page buffer is written in a page, which is a write destination, out of the pages of the storage medium.

Abstract: A memory controller includes an error check correction circuit performing a calculation regarding an error correction code of data, and a processor using the error check correction circuit and write the data with the error correction code to a non-volatile memory (NVM) when writing the data to the NVM, while performing error correction of the data using the error correction code when reading the data from the NVM. The processor counts the number of error bits of the data stored in a block that is a unit of batch-erasure of the data, stores the data in the block with a first error correction code having an error correction ability, and stores the data in the block with a second error correction code having an error correction ability higher than the first error correction code when the number of the error bits is larger than a value.

Abstract: A memory controller includes an error check correction circuit performing a calculation regarding an error correction code of data, and a processor using the error check correction circuit and write the data with the error correction code to a non-volatile memory (NVM) when writing the data to the NVM, while performing error correction of the data using the error correction code when reading the data from the NVM. The processor counts the number of error bits of the data stored in a block that is a unit of batch-erasure of the data, stores the data in the block with a first error correction code having an error correction ability, and stores the data in the block with a second error correction code having an error correction ability higher than the first error correction code when the number of the error bits is larger than a value.

Abstract: An example of the invention is a memory device including a controller and a plurality of randomly accessible memories that are capable of storing user data from a host. The controller includes data management information managing correspondence relations between address areas to be designated by the host and the plurality of memories, and compression policy management information managing associations of the address areas to be designated by the host with priorities in compressing user data to be stored in the plurality of memories. The controller is configured to determine a compression policy associated with a designated address area included in an access request from the host based on a priority associated with the designated address area and information on free space of the plurality of memories.

Abstract: The transfer data amount between a server and storage is effectively reduced, and the broadband of an effective band between the server and the storage is realized. An interface device is located in a server module, and, when receiving a read request issued by a server processor, transmits a read command based on the read request to a storage processor. In a case where a reverse-conversion instruction to cause the interface device to perform reverse conversion of post-conversion object data acquired by converting object data of the read request is received from the storage processor, DMA to transfer post-conversion object data stored in the transfer source address on a storage memory to the transfer destination address on the server memory while reverse-converting the post-conversion object data is performed.

Abstract: A storage device provides a logical space based on a storage medium that is configured by a plurality of logical areas to the higher-level apparatus, and a base data range exists in the storage medium for each logical area. The storage device reads the base data from the base data range that is corresponded to a write destination logical area to which the write destination logical address belongs, and creates difference data that is an exclusive OR of first data that is the base data and second data that is any one of data based on write data and the write data. The storage device creates compressed difference data by compressing the difference data, writes the compressed difference data to the storage medium, and associates a difference data range that is a range in which the compressed difference data has been written with the write destination logical area.

Abstract: The present invention guarantees throughput for decompressing compressed data. A data compression apparatus includes: a division unit that divides plaintext data inputted to the division unit into a plurality of plaintext blocks each having a prescribed plaintext block length; a compression unit that creates a payload for each plaintext block of the plurality of plaintext blocks by compressing the plaintext block using a sliding dictionary-type compression algorithm, creates a header indicating the length of the payload, and creates a compression block that includes the header and the payload; and a concatenation unit that creates compressed data by concatenating a plurality of compression blocks created from the plurality of plaintext blocks.

Abstract: The present invention guarantees throughput for decompressing compressed data. A data compression apparatus includes: a division unit that divides plaintext data inputted to the division unit into a plurality of plaintext blocks each having a prescribed plaintext block length; a compression unit that creates a payload for each plaintext block of the plurality of plaintext blocks by compressing the plaintext block using a sliding dictionary-type compression algorithm, creates a header indicating the length of the payload, and creates a compression block that includes the header and the payload; and a concatenation unit that creates compressed data by concatenating a plurality of compression blocks created from the plurality of plaintext blocks.

Abstract: A monitoring camera control terminal and a monitoring camera apparatus respectively correspond to a plurality of protocols defining messages instructing a variety of settings and operations between the monitoring camera control terminal and the monitoring camera apparatus, and the monitoring camera control terminal uses a first protocol to request the monitoring camera apparatus for information related to the monitoring camera apparatus, receives the requested information from the monitoring camera apparatus, and if the requested information does not match the setting or operation information recorded in a storage part of the monitoring camera control terminal, changes the first protocol to a second protocol.

Abstract: In a storage apparatus including a storage medium including a plurality of pages as a unit of reading and writing data, a first data block including a data block received from a higher-level device is generated, a second data block of a predetermined size including one or more undivided first data blocks is generated, a third data block in which a correction code is added to the second data block is generated, the third data block is stored in a page buffer, and one or more of the third data blocks stored in the page buffer is written in a page, which is a write destination, out of the pages of the storage medium.

Abstract: An example of the invention is a memory device including a controller and a plurality of randomly accessible memories that are capable of storing user data from a host. The controller includes data management information managing correspondence relations between address areas to be designated by the host and the plurality of memories, and compression policy management information managing associations of the address areas to be designated by the host with priorities in compressing user data to be stored in the plurality of memories. The controller is configured to determine a compression policy associated with a designated address area included in an access request from the host based on a priority associated with the designated address area and information on free space of the plurality of memories.

Abstract: The transfer data amount between a server and storage is effectively reduced, and the broadband of an effective band between the server and the storage is realized. An interface device is located in a server module, and, when receiving a read request issued by a server processor, transmits a read command based on the read request to a storage processor. In a case where a reverse-conversion instruction to cause the interface device to perform reverse conversion of post-conversion object data acquired by converting object data of the read request is received from the storage processor, DMA to transfer post-conversion object data stored in the transfer source address on a storage memory to the transfer destination address on the server memory while reverse-converting the post-conversion object data is performed.

Abstract: The transfer data amount between a server and storage is effectively reduced, and the broadband of an effective band between the server and the storage is realized. An interface device is located in a server module, and, when receiving a read request issued by a server processor, transmits a read command based on the read request to a storage processor. In a case where a reverse-conversion instruction to cause the interface device to perform reverse conversion of post-conversion object data acquired by converting object data of the read request is received from the storage processor, DMA to transfer post-conversion object data stored in the transfer source address on a storage memory to the transfer destination address on the server memory while reverse-converting the post-conversion object data is performed.

Abstract: A storage apparatus comprises a storage unit configured to store data which is read/written by the host apparatus, a compression/expansion unit configured to compress the data using a predetermined algorithm to generate compressed data, and expand the compressed data, and a control unit configured to control writing of data to the storage unit, wherein the control unit is configured to manage, as compression block units, divided compressed data which is obtained by dividing compressed data compressed by the compression/expansion unit into predetermined units, and padding data.

Abstract: Systems and methods of performing a host write process are provided. W blocks are selected from the multiple blocks and W is a natural number. Write target data in accordance with a write command is written to the W next write destination pages which are included in the W blocks respectively. Each block selected is a block whose next write destination page is a first kind page. Each block consists of multiple pages. The multiple pages are two or more first kind pages and two or more second kind pages. Each second kind page is a page with a lower write performance than that of each first kind page.

Abstract: In a semiconductor memory computer equipped with a flash memory, use of backed-up data is enabled. The semiconductor memory computer includes an address conversion table for detecting physical addresses of at least two pages storing data by designating a logical address from one of logical addresses to be designated by a reading request. The semiconductor memory computer includes a page status register for detecting one page status allocated to each page, and page statuses to be detected include the at least following four statuses: (1) a latest data storage status, (2) a not latest data storage status, (3) an invalid data storage status, and (4) an unwritten status. By using the address conversion table and the page status register, at least two data s (latest data and past data) can be read for one designated logical address from a host computer.

Abstract: According to this invention, a highly reliable memory device that uses up a life of a flash memory can be provided. The memory device is a nonvolatile memory device including a plurality of memory cells, in which: each of the plurality of memory cells is an FET which includes a floating gate; the plurality of memory cells are divided into a plurality of deletion blocks; and the nonvolatile memory device reads data stored in a first deletion block, detects and corrects an error contained in the read data, stores, when the number of bits of the detected error exceeds a threshold, the corrected data in a second deletion block, sets a smaller value as the threshold as an error frequency detected in the first deletion block is higher, and sets a smaller value as the threshold as the number of deletion times executed in the first deletion block is larger.