Abstract: A X-bit Digital-to-Analog Converter (DAC) circuit includes an effective X/2-bit coarse DAC configured to produce a coarse bitstream (CBS) from a digital input DC1 using an nth order Sigma-Delta (??) modulator, and to provide a coarse current source based on the CBS, wherein X is an even integer and n is an integer; an effective X/2-bit fine DAC configured to produce a fine bitstream (FBS) from a digital input DC2 using a 1st order ?? modulator, and to provide a fine current source based on the FBS; and an output configured to form a voltage from the combination of the coarse current source and the fine current source.

Abstract: A controlled switch having N inputs and a single output (N?2) is switchable between N states. In each state a respective one of the inputs is connected to the single output. There are N sources of sub-streams of analog samples, each sub-stream composed of pairs of adjacent analog samples. Each source is coupled to a respective one of the inputs. In operation, the controlled switch is controlled by a control signal to switch between the N states. While the controlled switch is in any one of the states, a data transition occurs between two adjacent analog samples in the sub-stream whose source is coupled to the input that is connected to the single output. The single output yields the high-bandwidth analog signal. Any pair of adjacent analog samples in any one of the sub-streams substantially determines a corresponding pair of adjacent analog samples in the high-bandwidth analog signal.

Abstract: A semiconductor waveguide device includes a first semiconductor layer having a first surface, wherein the first surface comprises a first protrusion and a second protrusion collectively forming a first trench in the first semiconductor layer, a second semiconductor layer having a second surface opposing the first surface of the first semiconductor layer, and an insulator layer disposed between and in contact with the first surface and the second surface, wherein the first semiconductor layer, the second semiconductor layer, and the insulator layer form a semiconductor waveguide region, and wherein the first trench is configured to confine a mode of light beam propagation in the semiconductor waveguide region.

Abstract: Techniques and circuits are proposed to increase averaging in the clock recovery band based on an amount of channel overlap in receivers using excess bandwidth for clock recovery, to mitigate the impact of spectral energy leaking into an active channel of interest from an adjacent active channel and to improve the accuracy of the phase estimate of the received transmitted clock.

Abstract: A controlled transconductance circuit (CTC) is disclosed. The CTC includes (i) a transistor comprising a drain terminal, a gate terminal, and a transistor source terminal, (ii) a biasing circuit element connected between the transistor source terminal and a CTC source terminal, and a variable capacitor connected between the transistor source terminal and a constant voltage terminal where the constant voltage terminal is adapted to receive a constant voltage, and (iii) a CTC control terminal adapted to control a transconductance of the CTC by controlling a capacitance of the variable capacitor.

Abstract: Proposed digital on-chip jitter and phase noise measurement techniques and circuits are presented and include the use of a digitally controlled delay locked loop having very fine resolution but limited range to track the phase error between the tested device output clock and its reference clock. Some implementations employ a combination of a high-gain 1-bit phase detector, a digital accumulator and a fine digitally controlled delay element to track the accumulated phase difference between the reference clock and the device under test. Observing the accumulator output is an indication of the jitter and performing a Fast Fourier Transform of the accumulator output provides the phase noise of the device under test.

Abstract: Techniques and circuits are proposed to increase averaging in the clock recovery band based on an amount of channel overlap in receivers using excess bandwidth for clock recovery, to mitigate the impact of spectral energy leaking into an active channel of interest from an adjacent active channel and to improve the accuracy of the phase estimate of the received transmitted clock.

Abstract: Proposed digital on-chip jitter and phase noise measurement techniques and circuits are presented and include the use of a digitally controlled delay locked loop having very fine resolution but limited range to track the phase error between the tested device output clock and its reference clock. Some implementations employ a combination of a high-gain 1-bit phase detector, a digital accumulator and a fine digitally controlled delay element to track the accumulated phase difference between the reference clock and the device under test. Observing the accumulator output is an indication of the jitter and performing a Fast Fourier Transform of the accumulator output provides the phase noise of the device under test.

Abstract: A method for clock recovery that may include obtaining an output signal from a phase locked loop (PLL) device. The method may further include determining, using a digital phase detector, the output signal, and a transmitter clock signal, an amount of phase difference between the output signal and the transmitter clock signal. The method may further include filtering, using a phase rotator and a digital accumulator, a portion of the amount of phase difference from the output signal to generate a filtered signal.

Abstract: A method for clock recovery that may include obtaining an output signal from a phase locked loop (PLL) device. The method may further include determining, using a digital phase detector, the output signal, and a transmitter clock signal, an amount of phase difference between the output signal and the transmitter clock signal. The method may further include filtering, using a phase rotator and a digital accumulator, a portion of the amount of phase difference from the output signal to generate a filtered signal.

Abstract: A controlled transconductance circuit (CTC) is disclosed. The CTC includes (i) a transistor comprising a drain terminal, a gate terminal, and a transistor source terminal, (ii) a biasing circuit element connected between the transistor source terminal and a CTC source terminal, and a variable capacitor connected between the transistor source terminal and a constant voltage terminal where the constant voltage terminal is adapted to receive a constant voltage, and (iii) a CTC control terminal adapted to control a transconductance of the CTC by controlling a capacitance of the variable capacitor.

Abstract: A method for clock recovery that may include obtaining an output signal from a phase locked loop (PLL) device. The method may further include determining, using a digital phase detector, the output signal, and a transmitter clock signal, an amount of phase difference between the output signal and the transmitter clock signal. The method may further include filtering, using a phase rotator and a digital accumulator, a portion of the amount of phase difference from the output signal to generate a filtered signal.

Abstract: A method for filtering noise. The method may include obtaining an output signal from a phase locked loop (PLL) device. The method may include determining, using a digital phase detector and the output signal, an amount of PLL error produced by the PLL device. The method may include filtering, using a delay element and a digital filter, a portion of the amount of PLL error from the output signal to produce a filtered signal in response to determining the amount of PLL error produced by the PLL device.

Abstract: A method for filtering noise. The method may include obtaining an output signal from a phase locked loop (PLL) device. The method may include determining, using a digital phase detector and the output signal, an amount of PLL error produced by the PLL device. The method may include filtering, using a delay element and a digital filter, a portion of the amount of PLL error from the output signal to produce a filtered signal in response to determining the amount of PLL error produced by the PLL device.

Abstract: A method and system for multiplexing data signals is provided. A first circuit is operable to generate a plurality of serialized data signals and is operable to adjust a phase of at least one of the serialized data signals to adjust bit and byte alignment. A second circuit is coupled to the first circuit to receive the plurality of serialized data signals from the first circuit. The second circuit has a multiplexer operable to generate a multiplexed output signal from the received serialized data signals. The first circuit is further coupled to the second circuit by a back channel operable to carry information regarding bit alignment and byte alignment of the received serialized data signals.

Abstract: A method and system for multiplexing a plurality of serialized data signals in which a first integrated circuit device generates a plurality of serialized data signals. A second integrated circuit device is in electrical communication with the first integrated circuit device. The second integrated circuit device includes a multiplexer operable to generate a multiplexed output signal from the plurality of serialized data signals received from the first integrated circuit. A phase data and byte snapshot back channel is transmitted from the second integrated circuit device to the first integrated circuit device. The phase data and byte snapshot back channel carries phase data and periodic snapshots of the serialized data signals. The phase data and byte snapshot back channel is used by the first integrated circuit device to adjust the phase of each of the plurality of serialized data signals to preserve bit and byte alignment. Such a method and system can be implemented as a 4×10 Gbit/Sec.