Abstract: A resistance variable memory device including a vertical transistor includes an active pillar including a channel region, a source formed in one end of the channel region, and a lightly doped drain (LDD) region and a drain formed in the other end of the channel region, a first gate electrode formed to surround a periphery of the LDD region and having a first work function, and a second gate electrode formed to be connected to the first gate electrode and to surround the channel region and having a second work function that is higher than the first work function.

Abstract: A resistance variable memory device including a vertical transistor includes an active pillar including a channel region, a source formed in one end of the channel region, and a lightly doped drain (LDD) region and a drain formed in the other end of the channel region, a first gate electrode formed to surround a periphery of the LDD region and having a first work function, and a second gate electrode formed to be connected to the first gate electrode and to surround the channel region and having a second work function that is higher than the first work function.

Abstract: A semiconductor device having a fin gate that improves an operation current, and a method of manufacturing the same. The semiconductor device includes an active pillar formed on a semiconductor substrate, the active pillar including an inner region and an outer region surrounding the inner region, and a fin gate overlapping an upper surface and a lateral surface of the active pillar. The inner portion of the active pillar includes a first semiconductor layer having a first lattice constant, and the outer region of the active pillar includes a second semiconductor layer having a second lattice constant smaller than the first lattice constant.

Abstract: A variable resistance memory device includes a semiconductor substrate having a vertical transistor with a shunt gate that increases an area of a gate of the vertical transistor.

Abstract: A stack type memory device and a method of manufacturing the same are provided. The stack type memory device includes a semiconductor substrate, a plurality of active layers stacked on the semiconductor substrate, and a gate structure overlapping the plurality of active layers. The gate structure includes a side gate region overlapping sides of the plurality of active layers and a top gate region overlapping a top of an uppermost active layer.

Abstract: Provided are a variable resistive memory device, and methods of fabricating and driving the same. The variable resistive memory device includes a plurality of memory cells arranged in a first direction and in a second direction different from the first direction, each of the plurality of memory cells comprising a variable resistor and a selection device serially connected to the variable resistor. A common wiring is electrically connected to first ends of the plurality of memory cells to apply a common reference voltage. Each wiring line of a plurality of wiring lines is electrically connected to second ends of the plurality of memory cells arranged in the plurality of rows oriented in the first direction. A plurality of selection lines are respectively connected to the selection devices of the plurality of memory cells to select any one of the plurality of memory cells via the plurality of wiring lines.

Abstract: A variable resistance memory device includes a semiconductor substrate having a vertical transistor with a shunt gate that increases an area of a gate of the vertical transistor.

Abstract: A three-dimensional semiconductor device, a resistive variable memory device including the same, and a method of manufacturing the same are provided.

Abstract: A semiconductor device having a vertical channel, a variable resistive memory device including the same, and a method of manufacturing the same are provided. The semiconductor device having a vertical channel includes a vertical pillar formed on a semiconductor substrate and including an inner portion and an outer portion surrounding the inner portion, junction regions formed in the outer portion of the vertical pillar, and a gate formed to surround the vertical pillar. The inner portion of the vertical pillar has a lattice constant smaller than that of the outer portion of the vertical pillar.

Abstract: A 3-dimensional stack memory device includes a semiconductor substrate, a stacked active pattern configured so that a plurality of stripe shape active regions and insulation layers are stacked alternatively over the semiconductor substrate, a gate electrode formed in the stacked active pattern, a source and drain formed at both sides of the gate electrode in each of the plurality of active regions, a bit line formed on one side of the drain to be connected to the drain, a resistive device layer formed on one side of the source to be connected to the source, and a source line connected to the resistive device layer. The source is configured of an impurity region having a first conductivity type, and the drain is configured of an impurity region having a second conductivity type different from the first conductivity type.

Abstract: A 3D variable resistance memory device having a junction FET and a driving method thereof are provided. The variable resistance memory device includes a semiconductor substrate and a string selection switch formed on the semiconductor substrate. A channel layer is formed on the column string selection switch. A plurality of gates stacked along a length of the channel layer and each of the gates contacts an outer side of the channel layer. A variable resistance layer is formed on an inner side of the channel layer, and contacts the channel layer.

Abstract: A semiconductor device having a fin gate that improves an operation current, and a method of manufacturing the same. The semiconductor device includes an active pillar formed on a semiconductor substrate, the active pillar including an inner region and an outer region surrounding the inner region, and a fin gate overlapping an upper surface and a lateral surface of the active pillar. The inner portion of the active pillar includes a first semiconductor layer having a first lattice constant, and the outer region of the active pillar includes a second semiconductor layer having a second lattice constant smaller than the first lattice constant.

Abstract: A 3D variable resistance memory device having a junction FET and a driving method thereof are provided. The variable resistance memory device includes a semiconductor substrate and a string selection switch formed on the semiconductor substrate. A channel layer is formed on the column string selection switch. A plurality of gates stacked along a length of the channel layer and each of the gates contacts an outer side of the channel layer. A variable resistance layer is formed on an inner side of the channel layer, and contacts the channel layer.

Abstract: A 3D variable resistance memory device having a junction FET and a driving method thereof are provided. The variable resistance memory device includes a semiconductor substrate and a string selection switch formed on the semiconductor substrate. A channel layer is formed on the column string selection switch. A plurality of gates stacked along a length of the channel layer and each of the gates contacts an outer side of the channel layer. A variable resistance layer is formed on an inner side of the channel layer, and contacts the channel layer.

Abstract: A 3D variable resistance memory device having a junction FET and a driving method thereof are provided. The variable resistance memory device includes a semiconductor substrate and a string selection switch formed on the semiconductor substrate. A channel layer is formed on the column string selection switch. A plurality of gates stacked along a length of the channel layer and each of the gates contacts an outer side of the channel layer. A variable resistance layer is formed on an inner side of the channel layer, and contacts the channel layer.

Abstract: A resistance variable memory device including a vertical transistor includes an active pillar including a channel region, a source formed in one end of the channel region, and a lightly doped drain (LDD) region and a drain formed in the other end of the channel region, a first gate electrode formed to surround a periphery of the LDD region and having a first work function, and a second gate electrode formed to be connected to the first gate electrode and to surround the channel region and having a second work function that is higher than the first work function.

Abstract: A variable resistance memory device includes a plurality of cell gate electrodes extending in a first direction, wherein the plurality of cell gate electrodes are stacked in a second direction that is substantially perpendicular to the first direction. A gate insulating layer surrounds each cell gate electrode of the plurality of cell gate electrodes and a cell drain region is formed on two sides of the each cell gate electrode of the plurality of cell gate electrodes. A channel layer extends in the second direction along the stack of the plurality of cell gate electrodes, and a variable resistance layer contacting the channel layer.

Abstract: A resistance variable memory device including a vertical transistor includes an active pillar including a channel region, a source formed in one end of the channel region, and a lightly doped drain (LDD) region and a drain formed in the other end of the channel region, a first gate electrode formed to surround a periphery of the LDD region and having a first work function, and a second gate electrode formed to be connected to the first gate electrode and to surround the channel region and having a second work function that is higher than the first work function.

Abstract: A variable resistance memory device includes a plurality of cell gate electrodes extending in a first direction, wherein the plurality of cell gate electrodes are stacked in a second direction that is substantially perpendicular to the first direction. A gate insulating layer surrounds each cell gate electrode of the plurality of cell gate electrodes and a cell drain region is formed on two sides of the each cell gate electrode of the plurality of cell gate electrodes. A channel layer extends in the second direction along the stack of the plurality of cell gate electrodes, and a variable resistance layer contacting the channel layer.

Abstract: A variable resistance memory device includes a plurality of cell gate electrodes extending in a first direction, wherein the plurality of cell gate electrodes are stacked in a second direction that is substantially perpendicular to the first direction. A gate insulating layer surrounds each cell gate electrode of the plurality of cell gate electrodes and a cell drain region is formed on two sides of the each cell gate electrode of the plurality of cell gate electrodes. A channel layer extends in the second direction along the stack of the plurality of cell gate electrodes, and a variable resistance layer contacting the channel layer.