Patents by Inventor Nan-Chun Lin
Nan-Chun Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200273803Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first and a second active dies separately arranged, an insulating encapsulation at least laterally encapsulating the first and the second active dies, a redistribution layer disposed on the insulating encapsulation, the first and the second active dies, and a fine-pitched die disposed on the redistribution layer and extending over a gap between the first and the second active dies. The fine-pitched die has a function different from the first and the second active dies. A die connector of the fine-pitched die is connected to a conductive feature of the first active die through a first conductive pathway of the redistribution layer. A first connecting length of the first conductive pathway is substantially equal to a shortest distance between the die connector of the fine-pitched die and the conductive feature of the first active die.Type: ApplicationFiled: July 17, 2019Publication date: August 27, 2020Applicant: Powertech Technology Inc.Inventors: Hung-Hsin Hsu, Nan-Chun Lin, Shang-Yu Chang Chien
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Publication number: 20200273829Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes first dies, an insulating encapsulation laterally encapsulating the first dies, a second die disposed over the portion of the insulating encapsulation and at least partially overlapping the first dies, and a redistribution structure disposed on the insulating encapsulation and electrically connected to the first dies and the second die. A second active surface of the second die faces toward first active surfaces of the first dies. The redistribution structure includes a first conductive via disposed proximal to the first dies, and a second conductive via disposed proximal to the second die. The first and second conductive vias are electrically coupled and disposed in a region of the redistribution structure between the second die and one of the first dies. The first conductive via is staggered from the second conductive via by a lateral offset.Type: ApplicationFiled: July 25, 2019Publication date: August 27, 2020Applicant: Powertech Technology Inc.Inventors: Hung-Hsin Hsu, Shang-Yu Chang Chien, Nan-Chun Lin
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Patent number: 10756065Abstract: A method of fabricating a package structure including at least the following steps is provided. A carrier is provided. A first package is formed on the carrier. The first package is formed by at least the following steps. A first redistribution layer is formed on the carrier, wherein the first redistribution layer has a first surface and a second surface opposite to the first surface. A semiconductor die is bonded on the first surface of the first redistribution layer. The semiconductor die is electrically connected to the first redistribution layer through a plurality of conductive wires. An insulating material is formed to encapsulate the semiconductor die and the plurality of conductive wires.Type: GrantFiled: January 14, 2020Date of Patent: August 25, 2020Assignee: Powertech Technology Inc.Inventors: Shang-Yu Chang Chien, Hung-Hsin Hsu, Nan-Chun Lin
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Publication number: 20200152609Abstract: A method of fabricating a package structure including at least the following steps is provided. A carrier is provided. A first package is formed on the carrier. The first package is formed by at least the following steps. A first redistribution layer is formed on the carrier, wherein the first redistribution layer has a first surface and a second surface opposite to the first surface. A semiconductor die is bonded on the first surface of the first redistribution layer. The semiconductor die is electrically connected to the first redistribution layer through a plurality of conductive wires. An insulating material is formed to encapsulate the semiconductor die and the plurality of conductive wires.Type: ApplicationFiled: January 14, 2020Publication date: May 14, 2020Applicant: Powertech Technology Inc.Inventors: Shang-Yu Chang Chien, Hung-Hsin Hsu, Nan-Chun Lin
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Publication number: 20200126815Abstract: A manufacturing method of a package structure is described. The method includes at least the following steps. A carrier is provided. A semiconductor die and a sacrificial structure are disposed on the carrier. The semiconductor die is electrically connected to the bonding pads on the sacrificial structure through a plurality of conductive wires. As encapsulant is formed on the carrier to encapsulate the semiconductor die, the sacrificial structure and the conductive wires. The carrier is debonded, and at least a portion of the sacrificial structure is removed through a thinning process. A redistribution layer is formed on the semiconductor die and the encapsulant. The redistribution layer is electrically connected to the semiconductor die through the conductive wires.Type: ApplicationFiled: December 23, 2019Publication date: April 23, 2020Applicant: Powertech Technology Inc.Inventors: Han-Wen Lin, Hung-Hsin Hsu, Shang-Yu Chang Chien, Nan-Chun Lin
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Patent number: 10629559Abstract: A package structure including a semiconductor die, an insulating encapsulant, a dielectric layer, and a redistribution layer is provided. The semiconductor die has an active surface, a back surface opposite to the active surface, and a plurality of conductive bumps disposed on the active surface. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer is disposed on the he insulating encapsulant and electrically connected to the plurality of conductive bumps. The dielectric layer is disposed between the insulating encapsulant and the redistribution layer, wherein the dielectric layer encapsulates at least a portion of each of the plurality of conductive bumps.Type: GrantFiled: September 19, 2018Date of Patent: April 21, 2020Assignee: Powertech Technology Inc.Inventors: Shang-Yu Chang Chien, Hung-Hsin Hsu, Nan-Chun Lin
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Patent number: 10629554Abstract: A package structure includes a die, an encapsulant, a dam structure, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The encapsulant encapsulates sidewalls of the die. The encapsulant has a first surface and a second surface opposite to the first surface. The first surface is coplanar with the rear surface of the die. The second surface is located at a level height different from the active surface of the die. The dam structure is disposed on the active surface of the die. A top surface of the dam structure is substantially coplanar with the second surface of the encapsulant. The redistribution structure is over the encapsulant, the dam structure, and the die. The redistribution structure is electrically connected to the die.Type: GrantFiled: April 13, 2018Date of Patent: April 21, 2020Assignee: Powertech Technology Inc.Inventors: Nan-Chun Lin, Hung-Hsin Hsu
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Publication number: 20200091126Abstract: A semiconductor package including a plurality of first chips, a plurality of through silicon vias, a least one insulator, a first circuit structure and a first encapsulant is provided. The first chip electrically connected to the through silicon vias includes a sensing area on a first active surface, a first back surface and a plurality of through holes extending from the first back surface towards the first active surface. The insulator is disposed on the first active surfaces of the first chips. The first circuit structure disposed on the first back surfaces of the first chips and electrically connected to the through silicon vias. The first encapsulant, laterally encapsulating the first chips.Type: ApplicationFiled: November 19, 2019Publication date: March 19, 2020Applicant: Powertech Technology Inc.Inventors: Nan-Chun Lin, Hung-Hsin Hsu, Shang-Yu Chang Chien, Wen-Hsiung Chang
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Publication number: 20200091103Abstract: A package structure including a semiconductor die, an insulating encapsulant, a dielectric layer, and a redistribution layer is provided. The semiconductor die has an active surface, a back surface opposite to the active surface, and a plurality of conductive bumps disposed on the active surface. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer is disposed on the he insulating encapsulant and electrically connected to the plurality of conductive bumps. The dielectric layer is disposed between the insulating encapsulant and the redistribution layer, wherein the dielectric layer encapsulates at least a portion of each of the plurality of conductive bumps.Type: ApplicationFiled: September 19, 2018Publication date: March 19, 2020Applicant: Powertech Technology Inc.Inventors: Shang-Yu Chang Chien, Hung-Hsin Hsu, Nan-Chun Lin
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Patent number: 10593647Abstract: A package structure including first and second packages is provided. The first package includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, and a plurality of conductive wire segments. The semiconductor die has an active surface and a back surface. The insulating encapsulant encapsulates the semiconductor die. The first redistribution layer is disposed on the back surface of the semiconductor die and a bottom surface of the insulating encapsulant. The first redistribution layer has a first surface and a second surface opposite to the first surface. The second redistribution layer is disposed on the active surface of the semiconductor die. The plurality of conductive wire segments electrically connects the semiconductor die to the second redistribution layer and the first redistribution layer to the second redistribution layer. The second package is stacked on the second surface of the first redistribution layer over the first package.Type: GrantFiled: June 27, 2018Date of Patent: March 17, 2020Assignee: Powertech Technology Inc.Inventors: Shang-Yu Chang Chien, Hung-Hsin Hsu, Nan-Chun Lin
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Publication number: 20200075510Abstract: A semiconductor package including a semiconductor die, an insulating encapsulant, a passive component, such as a thin film capacitor, and a redistribution structure is provided. The semiconductor die includes an active surface and a plurality of conductive pads disposed on the active surface. The insulating encapsulant encapsulates the semiconductor die and exposes the active surface of the semiconductor die. The passive component is disposed on the active surface of the semiconductor die. The redistribution structure is disposed on the active surface of the semiconductor die electrically connected to the conductive pads of the semiconductor die and the passive component. A manufacturing method of a semiconductor package is also provided.Type: ApplicationFiled: August 30, 2018Publication date: March 5, 2020Applicant: Powertech Technology Inc.Inventors: Shang-Yu Chang Chien, Hung-Hsin Hsu, Nan-Chun Lin
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Publication number: 20200035614Abstract: A package structure including a frame structure, a die, an encapsulant, and a redistribution structure is provided. The frame structure has a cavity. The die is disposed in the cavity. The die has an active surface, a rear surface opposite to the active surface, a plurality of lateral sides connecting the active surface and the rear surface, and a plurality of connection pads disposed on the active surface. The encapsulant encapsulates at least a portion of the frame structure and lateral sides of the die. The redistribution structure is disposed on the encapsulant and the active surface of the die. The connection pads are directly in contact with the redistribution structure.Type: ApplicationFiled: July 30, 2018Publication date: January 30, 2020Applicant: Powertech Technology Inc.Inventors: Nan-Chun Lin, Hung-Hsin Hsu
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Publication number: 20200026127Abstract: A display device includes a display panel and an optical element. The display panel includes a non-display area and a display area. The optical element is disposed corresponding to the display panel and includes a main body portion and a positioning portion connected to the main body portion. The main body portion includes a first part corresponding to the non-display area and a second part corresponding to the display area. The first part has a first opening disposed adjacent to the positioning portion.Type: ApplicationFiled: July 9, 2019Publication date: January 23, 2020Inventors: Nan-Chun LIN, Jia-Ming LI
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Publication number: 20200006290Abstract: A package structure including first and second packages is provided. The first package includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, and a plurality of conductive wire segments. The semiconductor die has an active surface and a back surface. The insulating encapsulant encapsulates the semiconductor die. The first redistribution layer is disposed on the back surface of the semiconductor die and a bottom surface of the insulating encapsulant. The first redistribution layer has a first surface and a second surface opposite to the first surface. The second redistribution layer is disposed on the active surface of the semiconductor die. The plurality of conductive wire segments electrically connects the semiconductor die to the second redistribution layer and the first redistribution layer to the second redistribution layer. The second package is stacked on the second surface of the first redistribution layer over the first package.Type: ApplicationFiled: June 27, 2018Publication date: January 2, 2020Applicant: Powertech Technology Inc.Inventors: Shang-Yu Chang Chien, Hung-Hsin Hsu, Nan-Chun Lin
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Patent number: 10522512Abstract: A semiconductor package including an ultra-thin redistribution structure, a semiconductor die, a first insulating encapsulant, a semiconductor chip stack, and a second insulating encapsulant is provided. The semiconductor die is disposed on and electrically coupled to the ultra-thin redistribution structure. The first insulating encapsulant is disposed on the ultra-thin redistribution structure and encapsulates the semiconductor die. The semiconductor chip stack is disposed on the first insulating encapsulant and electrically coupled to the ultra-thin redistribution structure. The second insulating encapsulant is disposed on the ultra-thin redistribution structure and encapsulates the semiconductor chip stack and the first insulating encapsulant. A manufacturing method of a semiconductor package is also provided.Type: GrantFiled: May 2, 2018Date of Patent: December 31, 2019Assignee: Powertech Technology Inc.Inventors: Shang-Yu Chang Chien, Hung-Hsin Hsu, Nan-Chun Lin
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Publication number: 20190393200Abstract: A package structure includes a first redistribution structure, a die, a plurality of conductive sheets, a plurality of conductive balls, and a first encapsulant. The first redistribution structure has a first surface and a second surface opposite to the first surface. The die has a plurality of connection pads electrically connected to the first surface of the first redistribution structure. The conductive sheets are electrically connected to the first surface of the first redistribution structure. The conductive balls are correspondingly disposed on the conductive sheets and are electrically coupled to the first surface of the first redistribution structure through the conductive sheets. The first encapsulant encapsulates the die, the conductive sheets, and the conductive balls. The first encapsulant exposes at least a portion of each conductive ball.Type: ApplicationFiled: June 25, 2018Publication date: December 26, 2019Applicant: Powertech Technology Inc.Inventors: Shang-Yu Chang Chien, Hung-Hsin Hsu, Nan-Chun Lin
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Patent number: 10515936Abstract: A package structure includes a first redistribution structure, a die, a plurality of conductive sheets, a plurality of conductive balls, and a first encapsulant. The first redistribution structure has a first surface and a second surface opposite to the first surface. The die has a plurality of connection pads electrically connected to the first surface of the first redistribution structure. The conductive sheets are electrically connected to the first surface of the first redistribution structure. The conductive balls are correspondingly disposed on the conductive sheets and are electrically coupled to the first surface of the first redistribution structure through the conductive sheets. The first encapsulant encapsulates the die, the conductive sheets, and the conductive balls. The first encapsulant exposes at least a portion of each conductive ball.Type: GrantFiled: June 25, 2018Date of Patent: December 24, 2019Assignee: Powertech Technology Inc.Inventors: Shang-Yu Chang Chien, Hung-Hsin Hsu, Nan-Chun Lin
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Publication number: 20190378803Abstract: A package structure including at least one semiconductor chip, an insulating encapsulant, a conductive frame, a supporting frame, a conductive layer and a redistribution layer is provided. The at least one semiconductor chip has an active surface and a backside surface opposite to the active surface. The insulating encapsulant is encapsulating the at least one semiconductor chip. The conductive frame is surrounding the insulating encapsulant. The supporting frame is surrounding the conductive frame. The conductive layer is disposed on the backside surface of the semiconductor chip. The redistribution layer is disposed on and electrically connected to the active surface of the semiconductor chip.Type: ApplicationFiled: June 7, 2018Publication date: December 12, 2019Applicant: Powertech Technology Inc.Inventors: Shang-Yu Chang Chien, Hung-Hsin Hsu, Nan-Chun Lin
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Publication number: 20190341369Abstract: A semiconductor package including an ultra-thin redistribution structure, a semiconductor die, a first insulating encapsulant, a semiconductor chip stack, and a second insulating encapsulant is provided. The semiconductor die is disposed on and electrically coupled to the ultra-thin redistribution structure. The first insulating encapsulant is disposed on the ultra-thin redistribution structure and encapsulates the semiconductor die. The semiconductor chip stack is disposed on the first insulating encapsulant and electrically coupled to the ultra-thin redistribution structure. The second insulating encapsulant is disposed on the ultra-thin redistribution structure and encapsulates the semiconductor chip stack and the first insulating encapsulant. A manufacturing method of a semiconductor package is also provided.Type: ApplicationFiled: May 2, 2018Publication date: November 7, 2019Applicant: Powertech Technology Inc.Inventors: Shang-Yu Chang Chien, Hung-Hsin Hsu, Nan-Chun Lin
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Publication number: 20190319000Abstract: A package structure includes a die, an encapsulant, a dam structure, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The encapsulant encapsulates sidewalls of the die. The encapsulant has a first surface and a second surface opposite to the first surface. The first surface is coplanar with the rear surface of the die. The second surface is located at a level height different from the active surface of the die. The dam structure is disposed on the active surface of the die. A top surface of the dam structure is substantially coplanar with the second surface of the encapsulant. The redistribution structure is over the encapsulant, the dam structure, and the die. The redistribution structure is electrically connected to the die.Type: ApplicationFiled: April 13, 2018Publication date: October 17, 2019Applicant: Powertech Technology Inc.Inventors: Nan-Chun Lin, Hung-Hsin Hsu