Abstract: A package structure includes a redistribution structure, a die, an insulation encapsulation, a protection layer, and a plurality of conductive terminals. The redistribution structure has a first surface and a second surface opposite to the first surface. The die is electrically connected to the redistribution structure. The die has an active surface, a rear surface opposite to the active surface, and lateral sides between the active surface and the rear surface. The insulation encapsulation encapsulates lateral sides of the die and the first surface of the redistribution structure. The protection layer is disposed on the rear surface of the die and the insulation encapsulation. The conductive terminals are formed on the second surface of the redistribution structure.

Abstract: A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a redistribution structure, at least one package structure and a second encapsulant. The redistribution structure has a first surface and a second surface opposite to the first surface. The package structure is over the first surface and includes at least one die, a first encapsulant, a redistribution layer, and a plurality of second conductive terminals. The die has a plurality of first conductive terminals thereon. The first encapsulant encapsulates the die and exposes at least part of the first conductive terminals. The redistribution layer is over the first encapsulant and is electrically connected to the first conductive terminals. The second conductive terminals are electrically connected between the redistribution layer and the redistribution structure. The second encapsulant, encapsulates the package structure and exposes at least part of the second conductive terminals.

Abstract: A package structure includes a first redistribution structure, a chip, an insulation encapsulation and a protection layer. The first redistribution structure has a first surface and a second surface opposite to the first surface. The chip is disposed on the first surface of the first redistribution structure and has an active surface and a rear surface opposite to the active surface. The insulation encapsulation encapsulates the chip and the first surface of the first redistribution structure. The protection layer is directly disposed on the rear surface of the chip.

Abstract: A chip packaging method includes forming a first redistribution layer and a first dielectric layer on a first temporary carrier to generate a plurality of first conductive interfaces close to the first temporary carrier, each pair of neighboring first conductive interfaces having a first pitch; forming a second dielectric layer on a first portion of the first redistribution layer and the first dielectric layer so as to cover the first portion of the first redistribution layer and expose a second portion; and forming a second redistribution layer and a third dielectric layer over the second dielectric layer to generate a plurality of second conductive interfaces. A circuitry being formed by at least the first redistribution layer and the second redistribution layer and each pair of neighboring second conductive interfaces has a second pitch larger than the first pitch.

Abstract: A conductive layer is formed on a first surface of a first carrier. The redistribution layer is formed on the conductive layer. Then an open-test is performed to the redistribution layer. Since the conductive layer and the redistribution layer constitute a closed loop, a load should be presented during the open-test if the redistribution layer is formed correctly. After the open-test is performed, the first carrier and the conductive layer are removed. Then a short-test is performed to the redistribution layer. No load is presented during the short-test if the redistribution layer is formed correctly since the redistribution layer constitutes an open loop. Therefore, whether the redistribution layer has flaws can be determined before the dies are boned on the redistribution layer. Thus, no waste of the good die occurs because of the flawed redistribution layer.

Abstract: A package structure includes a first redistribution layer, a second redistribution layer, a die, a plurality of conductive pillars and a die-stacked structure. The first redistribution layer has a first surface and a second surface opposite to the first surface. The second redistribution layer is disposed above the first surface. The die is disposed between the first redistribution layer and the second redistribution layer and has an active surface and a rear surface opposite to the active surface. The active surface is adhered to the first surface, and the die is electrically connected to the first redistribution layer. The conductive pillars are disposed and electrically connected between the first redistribution layer and the second redistribution layer. The die-stacked structure is bonded on the second redistribution layer.

Abstract: A manufacturing method of a packaging structure is provided. First, a carrier is provided. A conductive layer is formed on the carrier. A conductive frame is formed on the conductive layer. The conductive frame is in contact with and electrically connected to the conductive layer. A chip is placed on the conductive layer. The conductive frame surrounds the chip. An insulation encapsulation is formed to encapsulate the chip, and the insulation encapsulation exposes an active surface of the chip. A redistribution layer is formed on the active surface of the chip. The redistribution layer extends from the active surface to the insulation encapsulation.

Abstract: A manufacturing method of a package structure includes at least the following steps. A plurality of conductive connectors are formed on a circuit layer. The circuit layer includes a central region and a peripheral region electrically connected to the central region. A chip is disposed on the central region of the circuit layer. The chip includes an active surface at a distance from the circuit layer and a sensing area on the active surface. An encapsulant is formed on the circuit layer to encapsulate the chip and the conductive connectors. A redistribution layer is formed on the encapsulant to electrically connect the chip and the conductive connectors. The redistribution layer partially covers the chip and includes a window corresponding to the sensing area of the chip. A package structure is also provided.

Abstract: A conductive layer is formed on the first zone of a carrier. The redistribution layer is formed on the conductive layer on the first zone and the second zone of the carrier. Then an open-test and a short-test are performed to the redistribution layer. Since the conductive layer and the parts of the redistribution layer formed on the conductive layer constitute a closed loop, a load is presented if the redistribution layer is formed correctly. In addition, no load is presented if the redistribution layer is formed correctly since the parts of the redistribution layer formed on the second zone of the carrier constitute an open loop. Therefore, whether the redistribution layer is flawed or not is determined before the dies are boned on the redistribution layer. Thus, no waste of the good die is occurred because of the flawed redistribution layer.

Abstract: A chip package structure includes a semiconductor component, a plurality of conductive pillars, an encapsulant and a redistribution layer. The semiconductor component includes a plurality of pads. The conductive pillars are disposed on the pads, wherein each of the conductive pillars is a solid cylinder including a top surface and a bottom surface, and a diameter of the top surface is substantially the same as a diameter of the bottom surface. The encapsulant encapsulates the semiconductor component and the conductive pillars, wherein the encapsulant exposes the top surface of each of the conductive pillars. The redistribution layer is disposed on the encapsulant and electrically connected to the conductive pillars.

Abstract: A chip package structure includes a chip, an encapsulant, a dielectric layer and a patterned circuit layer. The chip includes an active surface and a plurality of pads disposed on the active surface. The encapsulant encapsulates the chip and exposes active surface, wherein the encapsulant includes a concave surface and a back surface opposite to the concave surface, the concave surface exposes the active surface and is dented toward the back surface. The dielectric layer covers the concave surface and the active surface and includes a plurality of openings exposing the pads, wherein the opening includes a slanted side surface and the angle between the slanted side surface and the active surface is an acute angle. The patterned circuit layer is disposed on the dielectric layer and electrically connected to the pads through the openings.

Abstract: A stacked-type chip package structure includes a first chip, first terminals, a first redistribution layer, a first encapsulant, a second chip, second terminals, a second redistribution layer and through pillars. Each first chip includes a first active surface and first pads located on the first active surface. The first terminals are disposed on the first pads. The first redistribution layer is electrically connected to the first chip. The first encapsulant encapsulates the first chip and exposes top surfaces of the first terminals. The second chip is disposed over the first encapsulant. The second chip includes a second active surface and second pads located on the second active surface. The second terminals are disposed on the second pads. The second redistribution layer is electrically connected to the second chip. The through pillars electrically connect the first redistribution layer and the second redistribution layer.

Abstract: A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a redistribution structure, at least one package structure and a second encapsulant. The redistribution structure has a first surface and a second surface opposite to the first surface. The package structure is over the first surface and includes at least one die, a first encapsulant, a redistribution layer, and a plurality of second conductive terminals. The die has a plurality of first conductive terminals thereon. The first encapsulant encapsulates the die and exposes at least part of the first conductive terminals. The redistribution layer is over the first encapsulant and is electrically connected to the first conductive terminals. The second conductive terminals are electrically connected between the redistribution layer and the redistribution structure. The second encapsulant, encapsulates the package structure and exposes at least part of the second conductive terminals.

Abstract: A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package includes a semiconductor substrate containing a chip and having a device area and a peripheral bonding pad area. A plurality of conductive pads is disposed at the peripheral bonding pad area and a passivation layer is formed over the semiconductor substrate to expose the conductive pads. An insulating protective layer is formed on the passivation layer at the device area. A packaging layer is disposed over the insulating protective layer to expose the conductive pads and the passivation layer at the peripheral bonding pad area. The method includes forming an insulating protective layer to cover a plurality of conductive pads during a cutting process and removing the insulating protective layer on the conductive pads through an opening of a packaging layer.

Abstract: An optoelectronic package includes an optoelectronic chip, a transparent protection layer and a plurality of pads. The optoelectronic chip has an upper surface and an active area defined on the upper surface. The transparent protection layer is connected to the optoelectronic chip and covers the upper surface. The transparent protection layer touches and is entirely attached to the active area. The pads are electrically connected to the optoelectronic chip.

Abstract: An optoelectronic package includes an optoelectronic chip, a transparent protection layer and a plurality of pads. The optoelectronic chip has an upper surface and an active area defined on the upper surface. The transparent protection layer is connected to the optoelectronic chip and covers the upper surface. The transparent protection layer touches and is entirely attached to the active area. The pads are electrically connected to the optoelectronic chip.

Abstract: An optoelectronic package includes an optoelectronic chip, a transparent protection layer and a plurality of pads. The optoelectronic chip has an upper surface and an active area defined on the upper surface. The transparent protection layer is connected to the optoelectronic chip and covers the upper surface. The transparent protection layer touches and is entirely attached to the active area. The pads are electrically connected to the optoelectronic chip.

Abstract: A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package includes a semiconductor substrate containing a chip and having a device area and a peripheral bonding pad area. A plurality of conductive pads is disposed at the peripheral bonding pad area and a passivation layer is formed over the semiconductor substrate to expose the conductive pads. An insulating protective layer is formed on the passivation layer at the device area. A packaging layer is disposed over the insulating protective layer to expose the conductive pads and the passivation layer at the peripheral bonding pad area. The method includes forming an insulating protective layer to cover a plurality of conductive pads during a cutting process and removing the insulating protective layer on the conductive pads through an opening of a packaging layer.

Abstract: A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package includes a semiconductor substrate containing a chip and having a device area and a peripheral bonding pad area. A plurality of conductive pads is disposed at the peripheral bonding pad area and a passivation layer is formed over the semiconductor substrate to expose the conductive pads. An insulating protective layer is formed on the passivation layer at the device area. A packaging layer is disposed over the insulating protective layer to expose the conductive pads and the passivation layer at the peripheral bonding pad area. The method includes forming an insulating protective layer to cover a plurality of conductive pads during a cutting process and removing the insulating protective layer on the conductive pads through an opening of a packaging layer.

Abstract: An optoelectronic package includes an optoelectronic chip, a transparent protection layer and a plurality of pads. The optoelectronic chip has an upper surface and an active area defined on the upper surface. The transparent protection layer is connected to the optoelectronic chip and covers the upper surface. The transparent protection layer touches and is entirely attached to the active area. The pads are electrically connected to the optoelectronic chip.