Patents by Inventor Nan Wang

Nan Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250017920
    Abstract: The present disclosure provides a magnetic nano-drug with double targeting vascular endothelial growth factor (VEGF)-vascular endothelial growth factor receptor (VEGFR), and a preparation method and application thereof, and belongs to the technical field of biomedicine. The magnetic nano-drug of the present disclosure includes aminated ZnFe2O4 hollow porous magnetic nano-particles, lactate dehydrogenase-silk fibroin (LDH-SF), ethylene dichloride (EDC), and n-hydroxy succinimide (NHS). A mass ratio of the aminated ZnFe2O4 hollow porous magnetic nano-particles to the EDC to the NHS to the LDH-SF is (5-10):(1-5):(1-6):(1-8). The magnetic nano-drug according to the present disclosure can position a VEGF ligand through magnetic targeting of hollow zinc ferrite particles, use magnetic particles to regulate reprogramming of macrophages in an intervertebral disc so as to indirectly regulate down-regulation of the VEGF, and inhibit angiogenesis.
    Type: Application
    Filed: July 8, 2024
    Publication date: January 16, 2025
    Inventors: Xin LIU, Ran KANG, Lin XIE, Congyang XUE, Bo CHEN, Zihan WANG, Nan WANG, Liping CHEN
  • Publication number: 20250013492
    Abstract: The present disclosure discloses a computing apparatus, a method for processing data using the computing apparatus, and related products. The computing apparatus is included in a combined processing apparatus. The combined processing apparatus further includes an interface apparatus and other processing apparatus. The computing apparatus interacts with other processing apparatus to jointly complete a user specified computation operation. The combined processing apparatus further includes a storage apparatus. The storage apparatus is connected to the computing apparatus and other processing apparatus, respectively. The storage apparatus is used to store data of the computing apparatus and other processing apparatus. The scheme of the present disclosure achieves task slicing on a single core or multiple cores in the convolution operation, which improves the computational efficiency.
    Type: Application
    Filed: June 22, 2022
    Publication date: January 9, 2025
    Applicant: Cambricon (Xi'an) Semiconductor Co., Ltd.
    Inventors: Linhui XIAO, Liutao ZHENG, Nan WANG, Xin YU
  • Patent number: 12164675
    Abstract: A capability management method and apparatus, a computer device, and the like relate to permission management of a kernel object in an operating system, for example, permission management of a kernel object in a microkernel architecture. In the method, two types of information are stored in a capability node of a capability owner: information used to indicate that a capability is granting and information used to indicate a granted capability. A capability association relationship between a grantor and a grantee is established by recording the two types of information, so that capability copying is avoided in a capability granting procedure, and capability deletion is avoided in a procedure of rejecting a capability by the grantee, thereby ensuring a deterministic latency while implementing capability revocation and granting. The method may be applied to a smartphone system, an unmanned driving system, or the like.
    Type: Grant
    Filed: May 2, 2022
    Date of Patent: December 10, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Nan Wang, Zipeng Zhang
  • Patent number: 12164137
    Abstract: The present disclosure provides a light guide plate, including a light-entering surface, a light-exiting surface adjacent to the light-entering surface, and a bottom surface arranged opposite to the light-exiting surface. The light guide plate includes a central region corresponding to an active display region of a display panel and a peripheral region corresponding a non-display region of the display panel in a first direction, the peripheral region includes a first peripheral region at a side adjacent to the light-entering surface, at least the first peripheral region of the peripheral region has a thickness smaller than the central region in a second direction, the first direction is a direction in which light is propagated inside the light guide plate, and the second direction is a direction in which the light exits the light guide plate. The present disclosure further provides a backlight module and a display device.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: December 10, 2024
    Assignees: Chongqing BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Xinlei Wang, Yong Shu, Nan Wang, Qi Cao, Ming Wang
  • Publication number: 20240405069
    Abstract: A method includes forming first nanostructures over a first region of a substrate; forming second nanostructures over a second region of the substrate; forming a first gate structure around the first nanostructures; replacing the second nanostructures with isolation regions; and forming a through via extending through isolation regions and into the substrate.
    Type: Application
    Filed: October 31, 2023
    Publication date: December 5, 2024
    Inventors: Chih Hsin Yang, Mao-Nan Wang, Dian-Hau Chen
  • Publication number: 20240363492
    Abstract: Semiconductor structures and methods for forming the same that include a through substrate via. Sacrificial gate structures are formed concurrently with active gate structures, the sacrificial gate structures being disposed in a through via region of the substrate. The sacrificial gate structures are subsequently removed from the substrate and dielectric material formed in their place. The through substrate via extends through the dielectric material.
    Type: Application
    Filed: April 26, 2023
    Publication date: October 31, 2024
    Inventors: Yang-Hsin SHIH, Mao-Nan WANG, Chih-Hsin YANG, Liang-Wei WANG
  • Publication number: 20240353608
    Abstract: A backlight module includes a rear housing, a light guide plate and a light source. The rear housing includes a bottom wall and a side wall that are connected to each other; the bottom wall and the side wall enclose an accommodation cavity. The light guide plate is located in the accommodation cavity. The light source is located in the accommodation cavity and located between the side wall and a side surface of the light guide plate. The light source includes a circuit board and a plurality of light-emitting devices that are mounted on the circuit board. A surface of the circuit board away from the plurality of light-emitting devices faces the side wall, and light-emitting surfaces of the plurality of light-emitting devices face the side surface of the light guide plate.
    Type: Application
    Filed: June 29, 2022
    Publication date: October 24, 2024
    Applicants: Chongqing BOE Optoelectronics Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Nan WANG, Yong SHU, Qi CAO, Xian WANG, Ming WANG, Quan TONG, Yinggang LIU, Chengyi XU, Xiaofei ZHU, Junjie JIANG
  • Publication number: 20240355911
    Abstract: A semiconductor device includes a substrate, a plurality of fins discretely arranged on the substrate, a connecting layer on sidewalls of the plurality of fins and between adjacent fins, and a gate structure across the plurality of fins and the connecting layer on the substrate. A top surface of the connecting layer is coplanar with a top surface of the plurality of fins. Each fin of the plurality of fins includes one or more channel layers spaced apart from each other. Each of the one or more channel layers is surrounded by the gate structure.
    Type: Application
    Filed: July 3, 2024
    Publication date: October 24, 2024
    Inventor: Nan WANG
  • Publication number: 20240354632
    Abstract: A method and an apparatus for generating a target deep learning model are provided. In the method, an instruction and original data for generating the target deep learning model is obtained from a user. The instruction includes a task expected to be performed by the target deep learning model. Then, training data is generated from the original data. A first deep learning model corresponding to the task is determined. Then, the first deep learning model is trained with the training data to obtain the target deep learning model.
    Type: Application
    Filed: June 22, 2022
    Publication date: October 24, 2024
    Applicants: JINA AI GMBH, JINA AI (BEIJING) CO., LTD.
    Inventors: Han XIAO, Nan WANG, Bo WANG, Werk MAXIMILIAN, Mastrapas GEORGIOS
  • Publication number: 20240347488
    Abstract: A chip structure is provided. The chip structure includes a semiconductor substrate. The chip structure includes a first conductive layer over the first dielectric layer. The chip structure includes a conductive via passing through the first conductive layer and electrically connected to the first conductive layer. The chip structure includes a conductive pad over and in direct contact with the conductive via. The chip structure includes a second conductive layer over and spaced apart from the first conductive layer. The chip structure includes a first dielectric layer conformally covering a second lower portion of a sidewall of the second conductive layer. The chip structure includes a third conductive layer over the first dielectric layer.
    Type: Application
    Filed: June 25, 2024
    Publication date: October 17, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Fan HUANG, Mao-Nan WANG, Hui-Chi CHEN, Dian-Hau CHEN, Yen-Ming CHEN
  • Publication number: 20240330681
    Abstract: A device for optimizing parameters of a deep neural network is included in an integrated circuit apparatus. The integrated circuit apparatus includes a general interconnection interface and other processing apparatus. A computing apparatus interacts with other processing apparatus to jointly complete a computing operation specified by a user. The integrated circuit apparatus further includes a storage apparatus. The storage apparatus is connected to the computing apparatus and other processing apparatus, respectively. The storage apparatus is used for data storage of the computing apparatus and other processing apparatus.
    Type: Application
    Filed: June 7, 2022
    Publication date: October 3, 2024
    Inventors: Xin YU, Yehao YU, Nan WANG, Yanjun ZHAO, Lingdong WU, Yongwei ZHAO, Yimin ZHUANG, Xiaobing CHEN
  • Patent number: 12103294
    Abstract: Heat sink and method of manufacturing a graphene based heat sink, the method comprising: providing a first and second graphene film; arranging a layer of nanoparticles on a surface of the first and second graphene film to improve an adhesion strength between the graphene films; attaching the second graphene film to the first graphene film by means of an adhesive and the layer of nanoparticles; forming a laminated graphene film comprising a number of graphene film layers by repeating the steps, wherein the laminated graphene film is formed to have an anisotropic thermal conductivity; assembling a plurality of laminated graphene films by applying pressure and heat to cure the adhesive to form a graphene block; and removing selected portions of the graphene block to form a heat sink comprising fins extending from a base plate of the heat sink.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: October 1, 2024
    Assignee: SHT Smart High-Tech AB
    Inventors: Johan Liu, Nan Wang
  • Publication number: 20240320500
    Abstract: A method and an apparatus for generating training data are provided. The training data is used for training a target deep learning model. In the method, original data for generating the target deep learning model is obtained from a user. Then, a type of the original data is determined. The type of the original data includes categorical data with label, session data with label, and data without label. A label of the categorical data indicates a category of the categorical data. A label of the session data indicates a question-answer relevance of the session data. Next, the training data is generated according to the type of the original data.
    Type: Application
    Filed: June 22, 2022
    Publication date: September 26, 2024
    Applicants: JINA AI GMBH, JINA AI (BEIJING) CO., LTD.
    Inventors: Han XIAO, Nan WANG, Bo WANG, Werk MAXIMILIAN, Mastrapas GEORGIOS
  • Patent number: 12089331
    Abstract: A metal circuit structure based on a flexible printed circuit (FPC) contains: a substrate, a first metal layer attached on the substrate, a second metal layer formed on the first metal layer, and an intermediate layer defined between the first metal layer and the second metal layer. A first surface of the intermediate layer is connected with the first metal layer, and a second surface of the intermediate layer is connected with the second metal layer. The intermediate layer is made of a first material, the second metal layer is made of a second material, and the first material of the intermediate layer does not act with the second material of the second metal layer.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: September 10, 2024
    Assignee: APLUS SEMICONDUCTOR TECHNOLOGIES CO., LTD.
    Inventors: Cheng-Neng Chen, Sui-Ho Tsai, Yun-Nan Wang, Chiao-Hui Wang
  • Publication number: 20240288602
    Abstract: A method for jointly estimating soil profile salinity by using time-series remote sensing image is provided. The method includes following. First, soil profile sample (1 meter), EM38-MK2 soil conductivity data, and a long time series monthly average Sentinel-2 satellite remote sensing image data for describing the same object is obtained. Secondly, the salt content of the soil profile with a depth of 1 meter is obtained according to linear regression equation and profile salt content calculation formula. Then, indices based on the time-series monthly average Sentinel-2 images are obtained to serve as independent variables of modeling by using a random forest to screen the independent variables. Finally, the salt contents of soil profile at 1 meter of the sample points are used as dependent variables, a temporal convolution network regression model is used for estimating, and a distribution map of the salt contents of the soil profile of large-space-scale is obtained.
    Type: Application
    Filed: May 5, 2024
    Publication date: August 29, 2024
    Applicant: ZHEJIANG UNIVERSITY
    Inventors: Zhou SHI, Nan WANG, Jie PENG, Jie XUE
  • Publication number: 20240270719
    Abstract: Disclosed herein are crystalline forms of 2-(4-(4-(aminomethyl)-1-oxo-1,2-dihydrophthalazin-6-yl)-1-methyl-1H-pyrazol-5-yl)-4-chloro-6-cyclopropoxy-3-fluorobenzonitrile free base, pharmaceutically acceptable compositions comprising these crystalline forms, and methods for using these crystalline forms.
    Type: Application
    Filed: February 9, 2024
    Publication date: August 15, 2024
    Inventors: Michal Achmatowicz, Svitlana Kulyk, Christopher Ronald Smith, Nan Wang, Harsh Shah, Tian Xie, Qi Gao
  • Publication number: 20240273010
    Abstract: Embodiments of the present disclosure relate to a method, an electronic device, and a computer program product for testing. The method includes: obtaining code modification information, program error information, and test case information. The method further includes: selecting a first test case set associated with code modification records from the test case information according to the program error information. The method further includes: sorting multiple test cases in the first test case set to generate a test strategy for the code modification records. Embodiments of the present disclosure may select the best test case for current code fix to meet different test requirements and reduce the test time.
    Type: Application
    Filed: March 1, 2023
    Publication date: August 15, 2024
    Inventors: Nan Wang, Chi Chen, Yang Wu, Jing Ye
  • Patent number: 12057419
    Abstract: A method for forming a chip structure is provided. The method includes providing a semiconductor substrate, a first conductive line, and a first dielectric layer. The method includes forming a first conductive layer over the first dielectric layer. The method includes forming a second conductive layer over the first conductive layer. The method includes forming a second dielectric layer over the second conductive layer and the first conductive layer. The method includes forming a first through hole passing through the second dielectric layer, the first conductive layer, and the first dielectric layer. The method includes forming a first conductive structure in and over the first through hole.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: August 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Fan Huang, Mao-Nan Wang, Hui-Chi Chen, Dian-Hau Chen, Yen-Ming Chen
  • Patent number: 12051737
    Abstract: Semiconductor device and fabrication method are provided by providing initial fins discretely arranged on a substrate; forming an isolation structure on the substrate; forming a connecting layer on sidewalls of the initial fins and between adjacent initial fins; forming a dummy gate structure across the initial fins and the connecting layer on the substrate, covering sidewalls of the connecting layer and a portion of a top surface of the initial fins; forming grooves in the initial fins on both sides of the dummy gate structure, and forming source and drain doped layers in the grooves; forming a dielectric layer on the substrate, covering sidewalls of the dummy gate structure and the source and drain doped layers, that a top surface of the dielectric layer is flush with a top surface of the dummy gate structure; and removing the dummy gate structure to form a gate structure.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: July 30, 2024
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Nan Wang
  • Patent number: 12052344
    Abstract: A method for electing a representative node device for a blockchain system includes: receiving IP address information of a first node device, the first node device being in a candidate state for a representative node device; receiving, from the first node device, an IP address obtaining request for requesting IP address information of a representative node device; when the first node device is determined to be a representative node device of the blockchain system elected in a current election process, transmitting, to the first node device, an IP address list comprising IP address information of representative node devices elected in the current election process; and when the first node device is determined not to be a representative node device of the blockchain system elected in the current election process, skipping the IP address obtaining request.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: July 30, 2024
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Rui Guo, Maocai Li, Zongyou Wang, Haitao Tu, Li Kong, Kaiban Zhou, Changqing Yang, Nan Wang, Yong Ding, Yifang Shi