Patents by Inventor Nan Yang

Nan Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240250134
    Abstract: A method includes forming a gate electrode and a source/drain region over a bulk portion of a semiconductor substrate, forming a cut-metal-gate region to separate the gate electrode into a first portion and a second portion, forming a source/drain contact plug overlapping and electrically connected to the source/drain region, forming a first contact rail overlapping a portion of the cut-metal-gate region, removing the bulk portion of the semiconductor substrate, and etching the cut-metal-gate region to form a trench. A surface of the first contact rail is revealed to the trench. A via rail is formed in the trench, and the via rail is electrically connected to the source/drain region through the first contact rail.
    Type: Application
    Filed: May 8, 2023
    Publication date: July 25, 2024
    Inventors: Chun-Yuan Chen, Cheng-Chi Chuang, Chih-Hao Wang, Huan-Chieh Su, Kuo-Nan Yang
  • Publication number: 20240248129
    Abstract: A circuit board detection device includes a base, a stage assembly, a first gantry support, and a first probe assembly. The stage assembly is arranged on the base and includes a linear drive module, a rotary motor, and a platform. The platform is configured to carry a circuit board and can be driven by the linear drive module to move along a first axial direction. The platform can also be driven by the rotary motor to rotate relative to a first rotation axis. The first gantry support is fixed on the base and includes a first beam. The first beam extends along a second axial direction perpendicular to the first axial direction to span over the linear drive module, and includes a first probe guide rail. The first probe assembly is arranged on the first probe guide rail to be movable along the second axial direction.
    Type: Application
    Filed: January 8, 2024
    Publication date: July 25, 2024
    Applicant: MPI Corporation
    Inventors: Wen-Wei Lin, Wen-Chung Lin, Chia-Nan Chou, Huang-Huang Yang, Yu-Tse Wang, Wei-Heng Hung, Ya-Hung Lo, Shou-Jen Tsai, Fuh-Chyun Tang
  • Publication number: 20240250285
    Abstract: The invention provides a method for suppressing thermal runaway of lithium batteries, which is included a step of providing a lithium battery capable of performing charging and discharging, which includes an electrochemical reaction system. When the temperature of the lithium battery reaches to a predetermined temperature, a metal ion (A) and an amphoteric metal ion (B) are applied to the positive active material layer and the negative active material layer of the lithium battery to passivate the positive active material layer and the negative active material layer. The metal ion (A) is selected from a non-lithium alkali metal ion, an alkaline earth metal ion or a combination thereof to prevent the thermal runaway from occurring.
    Type: Application
    Filed: April 3, 2024
    Publication date: July 25, 2024
    Applicants: PROLOGIUM TECHNOLOGY CO., LTD., Prologium Holding Inc.
    Inventor: Szu-Nan YANG
  • Publication number: 20240243858
    Abstract: Provided are a transmission method, apparatus and system and a computer-readable storage medium. The transmission method includes creating an automatic repeat request process for a first packet; setting a lifetime for the automatic repeat request process; and sending the first packet.
    Type: Application
    Filed: March 28, 2024
    Publication date: July 18, 2024
    Inventors: Dan YANG, Ning WEI, Bo SUN, Nan LI, Zhiqiang HAN
  • Publication number: 20240243238
    Abstract: An optoelectronic semiconductor device is provided. The optoelectronic semiconductor device includes a substrate, a semiconductor stack located on the substrate; a first trench and a second trench provided in the semiconductor stack; a first insulating layer filling in the first trench and covering the semiconductor stack; a first metal layer covering the first insulating layer; a second metal layer covering the first insulating layer; and a second insulating layer located between the first metal layer and the first insulating layer, and between the second metal layer and the first insulating layer. A part of the second trench is uncovered by the first insulating layer and the second insulating layer.
    Type: Application
    Filed: January 16, 2024
    Publication date: July 18, 2024
    Inventors: Ya-Nan Lin, Shih-I Chen, Chun-Ming Wu, Chin-I Lin, Chun-Ru Yang
  • Patent number: 12039805
    Abstract: The present invention provides an offline handwriting individual recognition system and method. The method comprises: scanning the suspicious handwriting to obtain a first white light image and a first three-dimensional image, and scanning the sample handwriting to obtain a second white light image and a second three-dimensional image; pre-processing the first white light image and the second white light image to obtain a first pre-processed image and a second pre-processed image; extracting a first skeleton image and a second skeleton image from the first pre-processed image and the second pre-processed image; obtaining a first writing trajectory and a second writing trajectory according to the first skeleton image and the second skeleton image; extracting a first dynamic feature, a first three-dimensional feature, and a second dynamic feature, a second three-dimensional feature; processing to obtain a correlation coefficient, and obtaining an individual recognition result.
    Type: Grant
    Filed: November 29, 2019
    Date of Patent: July 16, 2024
    Inventors: Xiaohong Chen, Xu Yang, Yachen Wang, Nan Wang, Qimeng Lu
  • Patent number: 12040963
    Abstract: A method is applied to a ring link, where the ring link includes a first node, a second node, a third node, and a fourth node in sequence. According to the method, the first node receives first traffic, where the first node is a source node that sends the first traffic on the ring link; and the first node sends the first traffic to the third node, where two reachable paths with equal hop counts are included from the first node to the third node, the first node sends the first traffic to the third node on a preset first transmission path, the first transmission path passes through the second node, and the first transmission path is one of the two reachable paths with equal hop counts. This method can reduce computing load of nodes while implementing non-blocking switching of traffic between the nodes.
    Type: Grant
    Filed: September 13, 2023
    Date of Patent: July 16, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yan Zhao, Yibo Yang, Renjie Qu, Nan Li
  • Publication number: 20240234321
    Abstract: A conductive line structure includes: first and second offset sets of long pillars that are substantially coaxial on an intra-set basis; a third set of offset short pillars, the short pillars being: overlapping of long pillars in the first and second sets; and organized into groups of first quantities of the short pillars; each of the groups being overlapping of and electrically coupled between a pair of one of the long pillars in the first set and a one of the long pillars in the second set such that, in each of the groups, each short pillar being overlapping of and electrically coupled between the pair; and each long pillar in each of the first and second sets being overlapped by a second quantity of short pillars in the third set and being electrically coupled to same; and the first quantity being less than the second quantity.
    Type: Application
    Filed: February 1, 2024
    Publication date: July 11, 2024
    Inventors: Hiranmay BISWAS, Chi-Yeh YU, Kuo-Nan YANG, Chung-Hsing WANG, Stefan RUSU, Chin-Shen LIN
  • Publication number: 20240235699
    Abstract: A system and method for determining an error vector magnitude (EVM) of a polarized transmission from a device-under-test (DUT). A first signal transmitted by the DUT is received via a horizontally polarized receiver antenna, and a second signal transmitted by the DUT is received via a vertically polarized receiver antenna. The second signal is coherent with the first signal. The EVM is calculated based at least in part on the first signal and the second signal and a reference signal.
    Type: Application
    Filed: January 7, 2023
    Publication date: July 11, 2024
    Inventors: Gerardo Orozco, Thomas Deckert, Nan Yang
  • Patent number: 12033998
    Abstract: An integrated circuit includes a gated circuit configured to operate on at least a first or a second voltage, a header circuit coupled to the gated circuit, a first and second power rail on a back-side of a wafer, and a third power rail on a front-side of the wafer. The header circuit is configured to supply the first voltage to the gated circuit by the first power rail. The first power rail includes a first portion, a second portion and a third portion, the third portion being between the first portion and the second portion. The second power rail is configured to supply the second voltage to the gated circuit, and is between the first portion and the second portion. The third power rail includes a first set of conductors. Each of the first set of conductors being configured to supply a third voltage to the header circuit.
    Type: Grant
    Filed: August 1, 2023
    Date of Patent: July 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuang-Ching Chang, Jung-Chan Yang, Hui-Zhong Zhuang, Chih-Liang Chen, Kuo-Nan Yang
  • Publication number: 20240221973
    Abstract: A cable includes: plural wire groups; a first insulating layer covering the plurality of wire groups; a first shielding layer covering the first insulating layer; a second shielding layer covering the first shielding layer; an outer insulating layer covering the second shielding layer; and an inner support member disposed inside the first insulating layer; wherein the inner support member includes a plurality of grooves with equal cross-sectional areas, one side of each wire group is disposed in the groove and in close contact with the inner support member, the other side of each wire group is in close contact with the first insulating layer to fix the position of each wire group, and the inner support member is made of silicone.
    Type: Application
    Filed: December 26, 2023
    Publication date: July 4, 2024
    Inventors: YU GONG, XIAO-FEI LIU, A-NAN YANG, HAN-RUN XIE, LU-YU CHANG
  • Patent number: 12019972
    Abstract: A method of forming a semiconductor device including: providing a first circuit cell including a first pin cell; forming a connecting path originated from the first pin cell of the first circuit cell; performing an Electromigration (EM) checking process with a first parasitic capacitance of the first pin cell and a second parasitic capacitance of the connecting path by loading a loading capacitance file to determine whether the loading capacitance of the first pin cell is larger than a first predetermined capacitance; and substituting a second pin cell for the first pin cell when the loading capacitance of the first pin cell is larger than the first predetermined capacitance, wherein the second pin cell is different from the first pin cell.
    Type: Grant
    Filed: April 19, 2023
    Date of Patent: June 25, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Kuo-Nan Yang, Wan-Yu Lo, Chung-Hsing Wang, Hiranmay Biswas
  • Patent number: 12014982
    Abstract: An IC device includes first and second cells adjacent each other and over a substrate. The first cell includes a first IO pattern along a first track among a plurality of tracks in a first metal layer, the plurality of tracks elongated along a first axis and spaced from each other along a second axis. The second cell includes a plurality of conductive patterns along corresponding different tracks among the plurality of tracks in the first metal layer, each of the plurality of conductive patterns being an IO pattern of the second cell or a floating conductive pattern. The first metal layer further includes a first connecting pattern along the first track and connects the first IO pattern and a second IO pattern of the second cell. The second IO pattern is one of the plurality of conductive patterns of the second cell and is along the first track.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: June 18, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Yu Lin, Jung-Chan Yang, Hui-Zhong Zhuang, Sheng-Hsiung Chen, Kuo-Nan Yang, Chih-Liang Chen, Lee-Chung Lu
  • Patent number: 12002920
    Abstract: The invention provides a method for suppressing thermal runaway of lithium batteries, which is included a step of providing a lithium battery capable of performing charging and discharging, which includes an electrochemical reaction system. When the temperature of the lithium battery reaches to a predetermined temperature, a metal ion (A) and an amphoteric metal ion (B) are applied to the positive active material layer and the negative active material layer of the lithium battery to passivate the positive active material layer and the negative active material layer. The metal ion (A) is selected from a non-lithium alkali metal ion, an alkaline earth metal ion or a combination thereof to prevent the thermal runaway from occurring.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: June 4, 2024
    Assignees: PROLOGIUM TECHNOLOGY CO., LTD., PROLOGIUM HOLDING INC.
    Inventor: Szu-Nan Yang
  • Patent number: 11978873
    Abstract: The invention provides a battery module with cooling cartridge and battery system thereof. The cooling cartridge is utilized to be disposed between the battery units stacked in a single axis. The supporting portion of the cooling cartridge is directly contacted in a large area to the current collecting sheet of the battery unit. And the wing portions, extended from the two sides of the supporting portion, are directly contacted to the inner sidewalls of the metal housing. Therefore, a large-area heat dissipating path for the battery cell is provided, and the performance and stability of the battery cell are greatly improved.
    Type: Grant
    Filed: August 2, 2023
    Date of Patent: May 7, 2024
    Assignees: PROLOGIUM TECHNOLOGY CO., LTD., PROLOGIUM HOLDING INC.
    Inventors: Szu-Nan Yang, Meng-Hung Wu
  • Publication number: 20240143391
    Abstract: The present application discloses a dispatching and control cloud data processing method, device and system. The method includes the following operations: pilot node device acquires a global scheduling task, decomposes the global scheduling task to obtain scheduling tasks, issues the scheduling tasks to collaborative node device, acquires data collection ranges and data processing rules of the collaborative node devices, and delivers them to the collaborative node devices; the collaborative node devices receive and execute the scheduling tasks issued by the pilot node device; receives the data collection ranges and the data processing rules issued by the pilot node device, acquires, based on the scheduling tasks, collected data in the data collection ranges, processes the acquired collected data according to the data processing rules to obtain the processed data, uploads the processed data to the pilot node device; the pilot node device receives the processed data uploaded by the collaborative node devices.
    Type: Application
    Filed: August 12, 2021
    Publication date: May 2, 2024
    Inventors: Dapeng LI, Lixin LI, Qingbo YANG, Lei TAO, Yunhao HUANG, Fangchun DI, Xuri SONG, Xiaolin QI, Nan YANG, Can CUI, Wenyue XIA, Ruili YE, Shuzhou WU, Lin XIE, Zhoujie ZHANG
  • Publication number: 20240136596
    Abstract: The invention discloses a lithium battery structure and the electrode layer thereof. The lithium battery structure includes two battery units with the two negative active material layers being disposed in face-to-face arrangement. The negative current collector includes a conductive substrate with a plurality of through holes and an isolation layer. The isolation layer is covered on one surface of the conductive substrate and extended along the through holes to another surface to cover the edge of the openings of the through holes. It can be effectively avoided the lithium dendrites depositing near the openings of the through holes on the conductive substrate. Also, the face-to-face arrangement of the negative active material layers is effectively control the locations of the plated lithium dendrites. Therefore, the safety of the battery and the cycle life of the battery is greatly improved.
    Type: Application
    Filed: December 15, 2023
    Publication date: April 25, 2024
    Applicants: PROLOGIUM TECHNOLOGY CO., LTD., Prologium Holding Inc.
    Inventor: Szu-Nan YANG
  • Patent number: 11959346
    Abstract: A method for offshore dual-drive core drilling with three layers of casings under surge compensation is provided. According to the method, a drilling vessel is located at set latitude and longitude coordinates by a dynamic positioning system; drill pipes are stabilized by a seabed template; torques and drilling pressures can be transmitted during drilling of the casings by means of surge compensation of the casings at a wellhead; during drilling for sampling, the surge compensation can compensate to a certain extent for a change in water depth caused by rising or falling tides, or surge, thereby preventing the casings from colliding with equipment and ensuring the safety of wellhead operation; and the drilling of three layers of casings is achieved by means of dual driver heads to effectively protect a wellbore wall, such that high core-drilling rate and good core-drilling quality are achieved during drilling for sampling.
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: April 16, 2024
    Assignee: GUANGZHOU MARINE GEOLOGICAL SURVEY
    Inventors: Lieyu Tian, Wu Guo, Nan Yang, Zhanzhao Li
  • Publication number: 20240096803
    Abstract: An integrated circuit includes a device, a first interconnect structure disposed above the device and a second interconnect structure positioned below the device. The first interconnect structure includes multiple frontside metal layers. The second interconnect structure includes multiple backside metal layers, where each backside metal layer includes metal conductors routed according to diagonal routing. In some embodiments, a backside interconnect structure can include another backside metal layer that includes metal conductors routed according to mixed-Manhattan-diagonal routing. A variety of techniques can be used to route signals between metal conductors in the backside interconnect structure and cells on one or more frontside metal layers.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Hsiung Chen, Jerry Chang Jui Kao, Kuo-Nan Yang, Jack Liu
  • Patent number: 11935833
    Abstract: A method of forming an IC structure includes forming first and second power rails at a power rail level. First metal segments are formed at a first metal level above the power rail level. Each first metal segment of the plurality of first metal segments overlap one or both of the first power rail or the second power rail. First vias are formed between the power rail level and the first metal level. Second metal segments are formed at a second metal level above the first metal level. At least one second metal segment of the plurality of second metal segments overlaps the first power rail. At least one second metal segment of the plurality of second metal segments overlaps the second power rail. A plurality of second vias are formed between the first metal level and the second metal level.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hiranmay Biswas, Chi-Yeh Yu, Kuo-Nan Yang, Chung-Hsing Wang, Stefan Rusu, Chin-Shen Lin