Patents by Inventor Nan Yang

Nan Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12377646
    Abstract: A film peeling method is disclosed to peel off a film covered on the surface of an object. The method includes the steps of: setting a fulcrum located at outer side of the object; setting a lift-off position on the film; and picking up the film from the lift-off position with the fulcrum as the axis, and applying a circular traction force with a variable radius on the film for peeling off the film from the object. The film peeling method can peel off the film covered on the surface of the object by different peeling stages, to reduce the peeling path and reduce the force required for peeling the film, thereby reducing the peeling time and improving the peeling efficiency.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: August 5, 2025
    Assignee: PROLOGIUM TECHNOLOGY CO., LTD.
    Inventors: Szu-Nan Yang, Chia-Chien Hung, Jian-Hua Su
  • Patent number: 12380265
    Abstract: A method of forming an integrated circuit includes forming at least a first or a second set of devices in a substrate, forming an interconnect structure over the first or second set of devices, and depositing a set of conductive structures on the interconnect structure. The first and second set of devices are configured to operate on a first supply voltage. Forming the interconnect structure includes depositing a set of insulating layers over the first or second set of devices, etching the set of insulating layers thereby forming a set of trenches, depositing a conductive material within the set of trenches, thereby forming a set of metal layers, and forming a portion of a header circuit between a first and a second metal layer. The header circuit is configured to provide the first supply voltage to the first set of devices.
    Type: Grant
    Filed: July 18, 2023
    Date of Patent: August 5, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: John Lin, Chin-Shen Lin, Kuo-Nan Yang, Chung-Hsing Wang
  • Publication number: 20250245414
    Abstract: The present disclosure provides a method, which includes the following steps: obtaining a netlist of an integrated circuit (IC) design; performing an automatic placement and routing (APR) process on the netlist to generate a result layout diagram; and during each operation with the APR process, refining, using a machine-learning model, a power delivery network within a layout diagram generated at each operation within the APR process.
    Type: Application
    Filed: June 7, 2024
    Publication date: July 31, 2025
    Inventors: WEN-HAO CHEN, MING-CHI CHEN, KUO-NAN YANG, YI-KAN CHENG, CHUN-YAO KU
  • Patent number: 12370592
    Abstract: The disclosure discloses a convexity adjusting mechanism for a working roll of a straightening machine and relates to the field of plate straightening devices. The convexity adjusting mechanism for the working roll of the straightening machine comprises a transmission shaft, a plurality of convexity adjusters, working rolls and supporting rolls corresponding to each convexity adjuster. The transmission shaft, the supporting rolls and the working rolls are axially parallel; the convexity adjust comprises a sleeve, a cam and a controller; the cam is provided with a through hole, the sleeve is mounted in the through hole, and the cam is sleeved on the transmission shaft through the sleeve; the sleeve is connected with the controller, and one end of the sleeve is provided with a gripping clawt.
    Type: Grant
    Filed: April 27, 2025
    Date of Patent: July 29, 2025
    Assignee: TAIYUAN UNIVERSITY OF TECHNOLOGY
    Inventors: Yizhong Cao, Hao Yuan, Da Ha, Weirong Zhang, Nan Yang
  • Publication number: 20250210996
    Abstract: Disclosed in the present application are a power grid real-time scheduling optimization method and system, a computer device and a storage medium. The method comprises: acquiring power grid model parameters and power grid operation data; and according to the power grid model parameters and the power grid operation data, obtaining a power grid real-time scheduling adjustment strategy by means of a preset power grid real-time scheduling reinforcement learning training model. Massive operation data of a power grid and load flow calculation simulation technologies can be fused by means of reinforcement learning, and unlike a conventional algorithm, a complex and difficult-to-solve calculation model does not need to be established, so that rapid optimization adjustment of power grid real-time scheduling is achieved, the optimization adjustment cost is reduced, and the matching degree of power grid real-time scheduling and actual operation is improved.
    Type: Application
    Filed: July 19, 2023
    Publication date: June 26, 2025
    Inventors: Nan YANG, Yupeng HUANG, Lixin LI, Jinbo LIU, Yijun YU, Xuri SONG, Yadi LUO, Li LI, Xiaolin QI, Yi HAN, Chengjian QIU, Fengbin ZHANG, Xingwei LIU, Lei TAO, Fangchun DI, Sheng LIU, Deyue MEN, Zechen WEI
  • Publication number: 20250209249
    Abstract: An integrated circuit layout is provided. The integrated circuit layout includes one or more first cell rows partially extending across a space arranged for an integrated circuit layout along a first direction. Each of the one or more first cell rows has a first height along a second direction perpendicular to the first direction. The integrated circuit layout includes one or more third cell rows partially extending across the space along the first direction. Each of the one or more third cell rows has a second height along the second direction, the second height different from the first height.
    Type: Application
    Filed: March 17, 2025
    Publication date: June 26, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Hsiung Chen, Chun-Chen Chen, Shao-huan Wang, Kuo-Nan Yang, Chung-Hsing Wang, Ren-Zheng Liao, Meng-Xiang Lee
  • Publication number: 20250191807
    Abstract: A cable includes: two inner conductors arranged in parallel; and a sheath layer covering outside the two inner conductors, plural air holes being provided on the sheath layer; wherein the plural air holes are arranged at intervals and surround the two inner conductors as a whole, and there are no air holes between the two inner conductors.
    Type: Application
    Filed: December 9, 2024
    Publication date: June 12, 2025
    Inventors: YU GONG, Xiao-Fei Liu, A-Nan Yang, Han-Run Xie, Lu-Yu Chang
  • Patent number: 12322834
    Abstract: The invention provides a soft pack battery module and its electricity supply thereof. The battery units, which are independent and complete modules, are utilized to be contacted to each other to form the battery cell with the serial connection, the parallel connection or both. There only have charges transferred rather than electrochemical reactions occurred between the battery units. Also, the metallized plastic film package is utilized to pack the battery cell. The inner electrically-conductive area of the metallized plastic film package is directly contacted to the electric power outputs of the battery cell to form electrical connections. Therefore, the problems caused by the need for additional wires can be avoided and the surface area the current path of the battery cell can be maximized.
    Type: Grant
    Filed: February 9, 2022
    Date of Patent: June 3, 2025
    Assignees: PROLOGIUM TECHNOLOGY CO., LTD., PROLOGIUM HOLDING INC.
    Inventors: Szu-Nan Yang, Meng-Hung Wu
  • Publication number: 20250167120
    Abstract: A conductive line structure (in an integrated circuit (IC)) includes: in a first layer of metallization (M_first layer), M_first segments extending in a first direction and being aligned to M_first routing tracks, the M_first segments including first and second ones thereof; and in a second layer of metallization (M_second layer) over the M_first layer, M_second segments extending in a second direction perpendicular to the first direction and being aligned to M_second routing tracks, the M_second segments including first and second ones thereof correspondingly overlapping the first and second M_first segments; and the first and second M_first segments being aligned to different first and second ones of the M_first routing tracks; and relative to the first direction, the first and second M_first segments being separated by a first gap having a size substantially equal to or greater than a minimum permissible offset between co-track aligned M_first segments.
    Type: Application
    Filed: January 17, 2025
    Publication date: May 22, 2025
    Inventors: Hiranmay BISWAS, Chi-Yeh YU, Kuo-Nan YANG, Chung-Hsing WANG, Stefan RUSU, Chin-Shen LIN
  • Publication number: 20250162443
    Abstract: The invention relates to a system for a user-side energy storage sharing framework. A power energy scheduling optimization method comprises: establishing a user load model, an energy storage battery model and a user-to-user capacity sharing model; with a minimum electricity cost of a whole community as an objective optimization function, resolving optimal scheduling based on the function using a MILP algorithm as an optimization technique for power energy scheduling of a user-side energy storage sharing framework; and performing power energy scheduling for users according to a resolved result.
    Type: Application
    Filed: April 21, 2024
    Publication date: May 22, 2025
    Applicant: State Grid Nanjing Power Supply Company
    Inventors: Hai Qing GAN, Yucheng REN, Hangtong ZHANG, Kun CHEN, Baligen TALIHATI, Yu WANG, Nan YANG, Jie SONG, Yaojie SUN
  • Patent number: 12302642
    Abstract: An integrated circuit includes a first power rail on a back-side of a wafer and being configured to supply a first voltage, a header circuit coupled to the first power rail and being configured to supply the first voltage to the first power rail, a second and third power rail on the back-side of the wafer, a fourth power rail on a front-side of the wafer, and a fifth power rail on the back-side of the wafer. The second and third power rail being configured to supply a second voltage. The fourth power rail includes a first set of conductors configured to supply a third voltage to the header circuit. The fifth power rail is configured to supply the third voltage and is separated from the first power rail in a first and second direction, and is separated from the second and third power rail in the first direction.
    Type: Grant
    Filed: July 1, 2024
    Date of Patent: May 13, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuang-Ching Chang, Jung-Chan Yang, Hui-Zhong Zhuang, Chih-Liang Chen, Kuo-Nan Yang
  • Patent number: 12289422
    Abstract: An electronic device includes a display screen, a camera, and a first display buffer. The display screen includes a first display area and a second display area, and a material of a display screen corresponding to the second display area is a transparent material. The camera is disposed below the display screen and opposite to a second display area. The first display buffer is configured to store a display signal of the first display area and a display signal of the second display area, and send the display signal of the first display area to the first display area. The first display buffer is further configured to determine, based on whether the camera is started, whether to send the display signal of the second display area to the second display area.
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: April 29, 2025
    Assignee: HONOR DEVICE CO., LTD.
    Inventors: Nan Yang, Dan Wang
  • Publication number: 20250125071
    Abstract: A cable includes: a pair of core wires each including an inner conductor and an inner insulating layer covering the inner conductor; an insulating layer covering the pair of core wires; a shielding layer covering the insulating layer; and an outer layer covering the shielding layer; wherein the inner insulating layer includes a first inner insulating layer and a second inner insulating layer, the first inner insulating layer is made of solid material and covers the inner conductor by extrusion molding, the second inner insulating layer is made of foamed material and wraps the first inner insulating layer in a winding way, the insulating layer includes a first insulating layer and a second insulating layer, the first insulating layer covers the pair of core wires in a winding way, and the second insulating layer covers the first insulating layer by extrusion molding.
    Type: Application
    Filed: October 9, 2024
    Publication date: April 17, 2025
    Inventors: A-NAN YANG, HAN-RUN XIE, LU-YU CHANG
  • Publication number: 20250117563
    Abstract: One aspect of this description relates to an integrated circuit (IC) structure including a first layer and a second layer. The first layer includes a first metal structure coupled to a first power supply having a first voltage level and a second metal structure coupled to a second power supply having a second voltage level different from the first voltage level. The second layer is formed over the first layer. The second layer includes a first nano-sheet device coupled to the first metal structure and a second nano-sheet device adjacent to the first nano-sheet device. The second nano-sheet device is coupled to the second metal structure. A distance between the first nano-sheet device and the second nano-sheet device is less than a minimum n-well to n-well spacing.
    Type: Application
    Filed: December 16, 2024
    Publication date: April 10, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jack Liu, Kuo-Nan Yang
  • Publication number: 20250118673
    Abstract: Semiconductor devices are provided. A semiconductor device includes a power switch, a first power mesh and a second power mesh. The power switch has a first terminal and a second terminal. The first power mesh is directly connected to the first terminal of the power switch. The second power mesh is directly connected to the second terminal of the power switch. The first power mesh includes a first power rail over the power switch and extending in a first direction. The second power mesh includes a second power rail under the power switch and extending in the first direction. The first and second power rails are separated from each other.
    Type: Application
    Filed: December 17, 2024
    Publication date: April 10, 2025
    Inventors: Wan-Yu LO, Chin-Shen LIN, Chi-Yu LU, Kuo-Nan YANG, Chih-Liang CHEN, Chung-Hsing WANG
  • Publication number: 20250117564
    Abstract: A method of forming an integrated circuit device includes forming first segments extending in a first direction in a first conductive layer; forming second segments extending in the first direction in the first conductive layer, the forming the first and second segments including: interspersing the first and second segments relative to a second direction perpendicular to the first direction such that: the first segments are symmetrically spaced apart relative to each other, the second segments are symmetrically spaced apart relative to each other, and ones of the second segments are substantially asymmetrically spaced between corresponding adjacent ones of the first segments.
    Type: Application
    Filed: December 16, 2024
    Publication date: April 10, 2025
    Inventors: Hiranmay BISWAS, Chung-Hsing WANG, Chin-Shen LIN, Kuo-Nan YANG
  • Publication number: 20250118457
    Abstract: A cable includes: a core wire; a shielding layer covering the core wire; an insulating layer covering the shielding layer; and an outer layer covering the insulating layer; wherein the outer layer is an insulating paint.
    Type: Application
    Filed: September 30, 2024
    Publication date: April 10, 2025
    Inventors: A-NAN YANG, Han-Run Xie, Lu-Yu Chang
  • Patent number: 12272796
    Abstract: The invention discloses a lithium battery structure and the electrode layer thereof. The lithium battery structure includes two battery units with the two negative active material layers being disposed in face-to-face arrangement. The negative current collector includes a conductive substrate with a plurality of through holes and an isolation layer. The isolation layer is covered on one surface of the conductive substrate and extended along the through holes to another surface to cover the edge of the openings of the through holes. It can be effectively avoided the lithium dendrites depositing near the openings of the through holes on the conductive substrate. Also, the face-to-face arrangement of the negative active material layers is effectively control the locations of the plated lithium dendrites. Therefore, the safety of the battery and the cycle life of the battery is greatly improved.
    Type: Grant
    Filed: December 15, 2023
    Date of Patent: April 8, 2025
    Assignees: PROLOGIUM TECHNOLOGY CO., LTD., PROLOGIUM HOLDING INC.
    Inventor: Szu-Nan Yang
  • Patent number: 12254260
    Abstract: An integrated circuit layout is provided. The integrated circuit layout includes one or more first cell rows partially extending across a space arranged for an integrated circuit layout along a first direction. Each of the one or more first cell rows has a first height along a second direction perpendicular to the first direction. The integrated circuit layout includes one or more third cell rows partially extending across the space along the first direction. Each of the one or more third cell rows has a second height along the second direction, the second height different from the first height.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: March 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sheng-Hsiung Chen, Chun-Chen Chen, Shao-huan Wang, Kuo-Nan Yang, Chung-Hsing Wang, Ren-Zheng Liao, Meng-Xiang Lee
  • Publication number: 20250087082
    Abstract: Provided are a digital twinning method and system for a scene flow based on a dynamic trajectory flow, which belong to the field of traffic control. The method includes: extracting and identifying a target semantic trajectory with a detecting and tracking integrated multi-modal fusion and perception enhancement network; extracting road traffic semantics, so as to obtain a highly parameterized virtual road layout top view; obtaining a road layout traffic semantic grid encoding vector based on the virtual road layout top view; constructing a target coupling relation model; constructing a traffic force constraint model; constructing a long short term memory trajectory prediction network; predicting a motion trajectory of a target with the long short term memory trajectory prediction network, so as to obtain the predicted motion trajectory; and obtaining a digital twin of the scene flow based on trajectory extraction, semantic identification and the predicted motion trajectory.
    Type: Application
    Filed: March 22, 2023
    Publication date: March 13, 2025
    Inventors: Zhanwen LIU, Xing FAN, Shan LIN, Chao LI, Jun ZHAI, Yanming Fang, Songhua FAN, Zijian WANG, Nan YANG, Zhibiao XUE, Jin FAN, Juanru CHENG, Yuande JIANG, Litong ZHANG