Patents by Inventor Nan Yu

Nan Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10810263
    Abstract: A method for providing a visual representation of data stored in a database may include generating a graphic user interface configured to receive inputs for constructing a hierarchical measure based on the data stored in the database. An indication to add, to the hierarchical measure, a first measure and a second measure may be received via the graphic user interface. In response to the indication, the hierarchical measure may be constructed to include, based on the first measure being added prior to the second measure, the first measure as a parent measure and the second measure as a child measure. A first value of the first measure may correspond to an aggregate of at least a second value of the second measure. The graphic user interface may be updated to provide a visual representation of the hierarchical measure. Related systems and articles of manufacture are also provided.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: October 20, 2020
    Assignee: SAP SE
    Inventors: Cheng Yu Yao, Nan Xuan Wang, Henry Lo
  • Patent number: 10807104
    Abstract: The disclosure discloses wet electrostatic classification device for ultrafine powder based on rotating flow field, which belongs to the field of ultrafine powder classification equipment. The wet electrostatic classification device for ultrafine powder of the disclosure includes a cylinder body. The cylinder body is a hollow cavity. A material conveying shaft and a rotating shaft are disposed in the cylinder body. Outlets are formed in a circumferential wall of the cylinder body. A deceleration motor is mounted on the lower end through a machine frame. First electrode pieces are disposed on an inner wall. The spray head is mounted between the material conveying shaft and the rotating shaft. The rotating shaft is connected to the deceleration motor through a coupling. Second electrode pieces are disposed on outer walls of the material conveying shaft and the rotating shaft. The spray head is configured to spray a material into the cylinder body to form a rotating flow.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: October 20, 2020
    Assignee: JIANGNAN UNIVERSITY
    Inventors: Jianfeng Yu, Ran Huang, Zhihua Li, Junnan Yu, Xiangyang Zheng, Nan Jin, Zhiqiang Liu
  • Publication number: 20200328161
    Abstract: A chip package structure including a first chip, an encapsulant, a first redistribution layer, a second redistribution layer, a second chip, and a third chip is provided. The first chip has an active surface, a back side surface opposite to the active surface, a plurality of conductive vias, and a plurality of conductive connectors disposed on the back side surface. The encapsulant covers the active surface, the back side surface, and the conductive connectors. The encapsulant has a first encapsulating surface and a second encapsulating surface opposite to the first encapsulating surface. The first redistribution layer is disposed on the first encapsulating surface. The second redistribution layer is disposed on the second encapsulating surface. The second chip is disposed on the second redistribution layer. The third chip is disposed on the second redistribution layer. A manufacturing method of a chip package structure is also provided.
    Type: Application
    Filed: March 25, 2020
    Publication date: October 15, 2020
    Applicant: Powertech Technology Inc.
    Inventors: Nan-Chun Lin, Hung-Hsin Hsu, Shang-Yu Chang Chien
  • Publication number: 20200328144
    Abstract: A semiconductor package including a semiconductor chip, a conductive element disposed aside the semiconductor chip, a conductive via disposed on and electrically connected to the conductive element, an insulating encapsulation, and a first circuit structure disposed on the semiconductor chip and the conductive via is provided. A height of the conductive element is less than a height of the semiconductor chip. The insulating encapsulation encapsulates the semiconductor chip, the conductive element, and the conductive via. The conductive via is located between the first circuit structure and the conductive element, and the semiconductor chip is electrically coupled to the conductive via through the first circuit structure.
    Type: Application
    Filed: April 12, 2019
    Publication date: October 15, 2020
    Applicant: Powertech Technology Inc.
    Inventors: Wen-Jeng Fan, Shang-Yu Chang Chien, Nan-Chun Lin, Hung-Hsin Hsu
  • Publication number: 20200328497
    Abstract: An integrated antenna package structure including a chip, a circuit layer, an encapsulant, a coupling end, an insulating layer, a conductive connector, a dielectric substrate, and an antenna is provided. The circuit layer is electrically connected to the chip. The encapsulant is disposed on the circuit layer and covers the chip. The coupling end is disposed on the encapsulant. The insulating layer covers the coupling end. The insulating layer is not externally exposed. The conductive connector penetrates the encapsulant. The coupling end is electrically connected to the circuit layer by the conductive connection. The dielectric substrate is disposed on the encapsulant and covers the coupling end. The antenna is disposed on the dielectric substrate. A manufacturing method of an integrated antenna package structure is also provided.
    Type: Application
    Filed: September 6, 2019
    Publication date: October 15, 2020
    Applicant: Powertech Technology Inc.
    Inventors: Han-Wen Lin, Hung-Hsin Hsu, Shang-Yu Chang Chien, Nan-Chun Lin
  • Publication number: 20200328167
    Abstract: An integrated antenna package structure including a chip package and an antenna device is provided. The antenna device is disposed on the chip package. The chip package includes a chip, an encapsulant, a circuit layer, and a conductive connector. The encapsulant at least directly covers the back side of the chip. The circuit layer is disposed on the encapsulant and electrically connected to the chip. The conductive connector penetrates the encapsulant and is electrically connected to the circuit layer. The antenna device includes a dielectric body, a coupling layer, and an antenna layer. The dielectric body has a first dielectric surface and a second dielectric surface opposite to the first dielectric surface. The coupling layer is disposed on the second dielectric surface of the dielectric body. The antenna layer is disposed on the first dielectric surface of the dielectric body. The antenna layer is electrically connected to the conductive connector.
    Type: Application
    Filed: November 27, 2019
    Publication date: October 15, 2020
    Applicant: Powertech Technology Inc.
    Inventors: Shang-Yu Chang Chien, Hung-Hsin Hsu, Nan-Chun Lin
  • Patent number: 10804199
    Abstract: A method of fabricating interconnects in a semiconductor device is provided, which includes forming an interconnect layer with a plurality of first conductive lines formed of a first conductive material in a dielectric layer. At least one via opening is formed over the plurality of first conductive lines and an interconnect via formed of a second conductive material is formed in the via opening, wherein the formed interconnect via has a convex top surface.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: October 13, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Yongjun Shi, Ruilong Xie, Nan Fu, Chun Yu Wong
  • Patent number: 10796931
    Abstract: A manufacturing method of a package structure is described. The method includes at least the following steps. A carrier is provided. A semiconductor die and a sacrificial structure are disposed on the carrier. The semiconductor die is electrically connected to the bonding pads on the sacrificial structure through a plurality of conductive wires. As encapsulant is formed on the carrier to encapsulate the semiconductor die, the sacrificial structure and the conductive wires. The carrier is debonded, and at least a portion of the sacrificial structure is removed through a thinning process. A redistribution layer is formed on the semiconductor die and the encapsulant. The redistribution layer is electrically connected to the semiconductor die through the conductive wires.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: October 6, 2020
    Assignee: Powertech Technology Inc.
    Inventors: Han-Wen Lin, Hung-Hsin Hsu, Shang-Yu Chang Chien, Nan-Chun Lin
  • Patent number: 10791643
    Abstract: A button assembly of the present invention is configured in a communication equipment, characterized in that: the button assembly includes a button, a tray and at least an elastic arm. A surface of the button is recessed to form a holding groove. The tray is disposed with a locking hole and a locking groove. The elastic arm has a pedestal arranged in the holding groove. The pedestal is protruded outward to form an elastic bar. A free end of the elastic bar forms a bump corresponding to the locking hole. An outer edge of the free end of the elastic bar forms a locking block corresponding to the locking groove. Hence, the locking hole and the elastic arm are disposed to provide the button and the tray to be fixed or disengaged, so as to achieve an effect of saving space in assembling of internal components of the communication equipment.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: September 29, 2020
    Assignee: CHENG UEI PRECISION INDUSTRY CO., LTD.
    Inventors: Chih-Chiang Lin, Te-Hung Yin, Chun-Fu Lin, Sheng-Nan Yu
  • Publication number: 20200273803
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first and a second active dies separately arranged, an insulating encapsulation at least laterally encapsulating the first and the second active dies, a redistribution layer disposed on the insulating encapsulation, the first and the second active dies, and a fine-pitched die disposed on the redistribution layer and extending over a gap between the first and the second active dies. The fine-pitched die has a function different from the first and the second active dies. A die connector of the fine-pitched die is connected to a conductive feature of the first active die through a first conductive pathway of the redistribution layer. A first connecting length of the first conductive pathway is substantially equal to a shortest distance between the die connector of the fine-pitched die and the conductive feature of the first active die.
    Type: Application
    Filed: July 17, 2019
    Publication date: August 27, 2020
    Applicant: Powertech Technology Inc.
    Inventors: Hung-Hsin Hsu, Nan-Chun Lin, Shang-Yu Chang Chien
  • Publication number: 20200273829
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes first dies, an insulating encapsulation laterally encapsulating the first dies, a second die disposed over the portion of the insulating encapsulation and at least partially overlapping the first dies, and a redistribution structure disposed on the insulating encapsulation and electrically connected to the first dies and the second die. A second active surface of the second die faces toward first active surfaces of the first dies. The redistribution structure includes a first conductive via disposed proximal to the first dies, and a second conductive via disposed proximal to the second die. The first and second conductive vias are electrically coupled and disposed in a region of the redistribution structure between the second die and one of the first dies. The first conductive via is staggered from the second conductive via by a lateral offset.
    Type: Application
    Filed: July 25, 2019
    Publication date: August 27, 2020
    Applicant: Powertech Technology Inc.
    Inventors: Hung-Hsin Hsu, Shang-Yu Chang Chien, Nan-Chun Lin
  • Patent number: 10756065
    Abstract: A method of fabricating a package structure including at least the following steps is provided. A carrier is provided. A first package is formed on the carrier. The first package is formed by at least the following steps. A first redistribution layer is formed on the carrier, wherein the first redistribution layer has a first surface and a second surface opposite to the first surface. A semiconductor die is bonded on the first surface of the first redistribution layer. The semiconductor die is electrically connected to the first redistribution layer through a plurality of conductive wires. An insulating material is formed to encapsulate the semiconductor die and the plurality of conductive wires.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: August 25, 2020
    Assignee: Powertech Technology Inc.
    Inventors: Shang-Yu Chang Chien, Hung-Hsin Hsu, Nan-Chun Lin
  • Publication number: 20200262860
    Abstract: The present application relates to a method for the prevention or treatment of an abnormal cell proliferative disease in a mammal, wherein the method comprises administering to the mammal an effective amount of a 4?-thionucleoside compound or a pharmaceutically acceptable salt, ester, hydrate, solvate thereof, or racemate thereof, or a mixture thereof.
    Type: Application
    Filed: April 17, 2020
    Publication date: August 20, 2020
    Applicant: Sichuan Kelun-Biotech Biopharmaceutical Co., Ltd.
    Inventors: Hong Ye, Gang Liu, Nan Yu, Hong Zeng, Mingliang Zhao, Yan Qing, Hua Deng, Wenjia Li, Donghong Li, Donghai Su, Wei Zhong, Shaohua Li, Xunwei Wu, Lichun Wang, Jingyi Wang
  • Patent number: 10748706
    Abstract: A method for producing a sintered R-iron (Fe)-boron (B) magnet, the method including: (1) producing a sintered magnet R1-Fe—B-M, where R1 is neodymium (Nd), praseodymium (Pr), terbium (Tb), dysprosium (Dy), gadolinium (Gd), holmium (Ho), or a combination thereof; M is titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), cobalt (Co), nickel (Ni), gallium (Ga), calcium (Ca), copper (Cu), Zinc (Zn), silicon (Si), aluminum (Al), magnesium (Mg), zirconium (Zr), niobium (Nb), hafnium (Hf), tantalum (Ta), tungsten (W), molybdenum (Mo), or a combination thereof; (2) removing oil, washing using an acid solution, activating, and washing using deionized water the sintered magnet, successively; (3) mixing a superfine terbium powder, an organic solvent, and an antioxidant to yield a homogeneous slurry, coating the homogeneous slurry on the surface of the sintered magnet; and (4) sintering and aging the sintered magnet.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: August 18, 2020
    Assignee: YANTAI ZHENGHAI MAGNETIC MATERIAL CO., LTD.
    Inventors: Yongjiang Yu, Xiuyan Sun, Nan Zhao, Xiaodong Tian
  • Patent number: 10720702
    Abstract: A method for correcting antenna phases includes a beam angle calculating step, beam angle adjusting step, antenna emission measuring step and beam angle correcting step. The method involves comparing a difference between the ideal antenna phase value and the measured beam angle value, determining according to the difference that the beam direction of the antenna needs to be corrected, and adding the difference to a current ideal antenna phase value in the algorithm to calculate another ideal antenna phase value for being sent to the phase control circuit and used in executing the beam angle adjusting step in a next instance of measurement process until the beam angle correcting step finds the difference which requires no correction of the beam direction of the antenna. Therefore, temperature-dependent errors do not occur to beam directions, thereby enhancing the communication efficiency of an antenna system.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: July 21, 2020
    Assignee: NATIONAL CHUNG SHAN INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Hsi-Tseng Chou, Dun-Yuan Cheng, Kung-Yu Lu, Nan-Wei Chen, Ming-Whay Lai
  • Patent number: 10720477
    Abstract: There is provided an OLED array substrate, a production method thereof, and a display apparatus. This OLED array substrate comprises: a substrate; a plurality of pixel defining layers which are provided at intervals on the substrate; and a conductive structure which is at least partly located in at least one of the plurality of pixel defining layers.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: July 21, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Shengji Yang, Xue Dong, Xiaochuan Chen, Hui Wang, Yanming Wang, Fang Yu, Wei Li, Ming Yang, Pengcheng Lu, Nan Mu
  • Publication number: 20200214671
    Abstract: An ultrasonic scanning method for an ultrasonic scanning device is provided according to an embodiment of the disclosure. The ultrasonic scanning method includes: performing an ultrasonic scanning operation on a human body by an ultrasonic scanner to obtain an ultrasonic image; analyzing the ultrasonic image by an image recognition module to identify an organ pattern in the ultrasonic image; and generating, automatically, a guiding message according to an identification result of the organ pattern, wherein the guiding message is configured to guide a moving of the ultrasonic scanner to scan a target organ of the human body.
    Type: Application
    Filed: May 13, 2019
    Publication date: July 9, 2020
    Applicant: Acer Incorporated
    Inventors: Chun-Hsien Yu, Kuo-Nan Chen
  • Patent number: 10700202
    Abstract: A semiconductor device is disclosed. The semiconductor device comprises a substrate, a gate structure disposed on the substrate, a spacer disposed on the substrate and covering a sidewall of the gate structure, an air gap sandwiched between the spacer and the substrate, and a source/drain region disposed in the substrate and having a faceted surface exposed from the substrate, wherein the faceted surface borders the substrate on a boundary between the air gap and the substrate.
    Type: Grant
    Filed: October 28, 2018
    Date of Patent: June 30, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuang-Hsiu Chen, Sung-Yuan Tsai, Chi-Hsuan Tang, Kai-Hsiang Wang, Chao-Nan Chen, Shi-You Liu, Chun-Wei Yu, Yu-Ren Wang
  • Publication number: 20200183979
    Abstract: A method for providing a visual representation of data stored in a database may include generating a graphic user interface configured to receive inputs for constructing a hierarchical measure based on the data stored in the database. An indication to add, to the hierarchical measure, a first measure and a second measure may be received via the graphic user interface. In response to the indication, the hierarchical measure may be constructed to include, based on the first measure being added prior to the second measure, the first measure as a parent measure and the second measure as a child measure. A first value of the first measure may correspond to an aggregate of at least a second value of the second measure. The graphic user interface may be updated to provide a visual representation of the hierarchical measure. Related systems and articles of manufacture are also provided.
    Type: Application
    Filed: December 6, 2018
    Publication date: June 11, 2020
    Inventors: Cheng Yu Yao, Nan Xuan Wang, Henry Lo
  • Publication number: 20200176357
    Abstract: A semiconductor package includes a semiconductor package, a cap, a seal, and microstructures. The semiconductor package includes at least one semiconductor die. The cap is disposed over an upper surface of the semiconductor package. The seal is located on the semiconductor package and between the cap and the semiconductor package. The cap includes an inflow channel and an outflow channel. The active surface of the at least one semiconductor die faces away from the cap. The cap and an upper surface of the semiconductor package define a circulation recess providing fluidic communication between the inflow channel and the outflow channel. The seal is disposed around the circulation recess. The microstructures are located within the circulation recess, and the microstructures are connected to at least one of the cap and the at least one semiconductor die.
    Type: Application
    Filed: October 17, 2019
    Publication date: June 4, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Chun-Hui Yu, Jeng-Nan Hung, Kuo-Chung Yee