Patents by Inventor Nan-Yuan Huang
Nan-Yuan Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250240985Abstract: The invention provides a semiconductor structure with a deep trench capacitor structures, which comprises a substrate, the substrate comprises a bottle-shaped trench, wherein the bottle-shaped trench has an upper part and a lower part in a cross section, and the interface between the upper part and the lower part is a bottleneck line, wherein the bottleneck line is the part with the smallest width in the bottle-shaped trench, a first dielectric layer is filled in the bottle-shaped trench, and a void is located in the first dielectric layer, wherein the highest point of the void is lower than the bottleneck line.Type: ApplicationFiled: February 21, 2024Publication date: July 24, 2025Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yi-Fan Li, Nan-Yuan Huang, Kuan-Jhih Hou, Yu-Fu Wang, Ya-Yin Hsiao, Po-Ching Su, Ti-Bin Chen, Chih-Chiang Wu, Yao-Jhan Wang
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Publication number: 20250169140Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer adjacent to the gate structure, wherein the first spacer comprises silicon carbon nitride (SiCN); forming a second spacer adjacent to the first spacer, wherein the second spacer comprises silicon oxycarbonitride (SiOCN); and forming a source/drain region adjacent to two sides of the second spacer.Type: ApplicationFiled: January 15, 2025Publication date: May 22, 2025Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chia-Ming Kuo, Po-Jen Chuang, Yu-Ren Wang, Ying-Wei Yen, Fu-Jung Chuang, Ya-Yin Hsiao, Nan-Yuan Huang
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Patent number: 12237398Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer adjacent to the gate structure, wherein the first spacer comprises silicon carbon nitride (SiCN); forming a second spacer adjacent to the first spacer, wherein the second spacer comprises silicon oxycarbonitride (SiOCN); and forming a source/drain region adjacent to two sides of the second spacer.Type: GrantFiled: June 4, 2021Date of Patent: February 25, 2025Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Ming Kuo, Po-Jen Chuang, Yu-Ren Wang, Ying-Wei Yen, Fu-Jung Chuang, Ya-Yin Hsiao, Nan-Yuan Huang
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Publication number: 20210296466Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer adjacent to the gate structure, wherein the first spacer comprises silicon carbon nitride (SiCN); forming a second spacer adjacent to the first spacer, wherein the second spacer comprises silicon oxycarbonitride (SiOCN); and forming a source/drain region adjacent to two sides of the second spacer.Type: ApplicationFiled: June 4, 2021Publication date: September 23, 2021Inventors: Chia-Ming Kuo, Po-Jen Chuang, Yu-Ren Wang, Ying-Wei Yen, Fu-Jung Chuang, Ya-Yin Hsiao, Nan-Yuan Huang
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Patent number: 11063135Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer adjacent to the gate structure, wherein the first spacer comprises silicon carbon nitride (SiCN); forming a second spacer adjacent to the first spacer, wherein the second spacer comprises silicon oxycarbonitride (SiOCN); and forming a source/drain region adjacent to two sides of the second spacer.Type: GrantFiled: June 4, 2018Date of Patent: July 13, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Ming Kuo, Po-Jen Chuang, Yu-Ren Wang, Ying-Wei Yen, Fu-Jung Chuang, Ya-Yin Hsiao, Nan-Yuan Huang
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Publication number: 20200111802Abstract: A method of preventing charge loss from a floating gate includes providing a substrate comprising a memory cell region and a logic region, wherein a floating gate is disposed in the memory cell region and a gate structure is disposed within the logic region, a first hard mask covers the floating gate and a second hard mask covers the first hard mask. A planarization process is performed to remove entirely the second hard mask and expose the first hard mask. Later, a third hard mask is formed to cover the first hard mask, the gate structure and the substrate, wherein the third hard mask prevents charges in the floating gate from flowing to the first hard mask. Finally, the third hard mask within the logic region is removed and the third hard mask remains within the memory region.Type: ApplicationFiled: October 4, 2018Publication date: April 9, 2020Inventors: Nan-Yuan Huang, Cheng-Lin Peng, Lung-En Kuo, Li-Chieh Hsu
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Publication number: 20190348520Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer adjacent to the gate structure, wherein the first spacer comprises silicon carbon nitride (SiCN); forming a second spacer adjacent to the first spacer, wherein the second spacer comprises silicon oxycarbonitride (SiOCN); and forming a source/drain region adjacent to two sides of the second spacer.Type: ApplicationFiled: June 4, 2018Publication date: November 14, 2019Inventors: Chia-Ming Kuo, Po-Jen Chuang, Yu-Ren Wang, Ying-Wei Yen, Fu-Jung Chuang, Ya-Yin Hsiao, Nan-Yuan Huang
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Patent number: 10283415Abstract: A semiconductor structure includes a substrate, a plurality of fin shaped structures, a trench, and a first bump. The substrate has a base, and the fin shaped structures protrude from the base. The trench is recessed from the base of the substrate. The first bump is disposed within the trench and protrudes from a bottom surface of the trench. A width of the first bump is larger than a width of each of the fin shaped structures.Type: GrantFiled: September 16, 2018Date of Patent: May 7, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Te-Chang Hsu, An-Chi Liu, Nan-Yuan Huang, Yu-Chih Su, Cheng-Pu Chiu, Tien-Shan Hsu, Chih-Yi Wang, Chi-Hsuan Cheng
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Publication number: 20190043760Abstract: A semiconductor structure includes a substrate, a plurality of fin shaped structures, a trench, and a first bump. The substrate has a base, and the fin shaped structures protrude from the base. The trench is recessed from the base of the substrate. The first bump is disposed within the trench and protrudes from a bottom surface of the trench. A width of the first bump is larger than a width of each of the fin shaped structures.Type: ApplicationFiled: September 16, 2018Publication date: February 7, 2019Inventors: Te-Chang Hsu, An-Chi Liu, Nan-Yuan Huang, Yu-Chih Su, Cheng-Pu Chiu, Tien-Shan Hsu, Chih-Yi Wang, Chi-Hsuan Cheng
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Patent number: 10170624Abstract: A non-planar transistor is provided. It includes a substrate, a fin structure, a gate structure, a first spacer structure and a source/drain region. The fin structure is disposed on the substrate, the gate structure is disposed on the fin structure. The fin structure includes an upper portion, a concave portion and a lower portion, and the concave portion is disposed between the upper portion and the lower portion. The first spacer structure is disposed on a sidewall of the gate structure. The first spacer structure includes a first spacer and a second spacer, wherein the first spacer is disposed between the second spacer, and a height of the first spacer is different from a height of the second spacer. The source/drain region is disposed in a semiconductor layer at two sides of the first spacer structure.Type: GrantFiled: March 2, 2017Date of Patent: January 1, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Jhen-Cyuan Li, Nan-Yuan Huang, Shui-Yen Lu
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Patent number: 10121881Abstract: A semiconductor device preferably includes a substrate, a fin-shaped structure on the substrate, a buffer layer on the fin-shaped structure, and an epitaxial layer on the buffer layer. Preferably, the buffer layer is made of silicon germanium and including three or more than three elements. The buffer layer also includes dopants selected from the group consisting of P, As, Sb, Bi, C, and F.Type: GrantFiled: April 6, 2017Date of Patent: November 6, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Li-Wei Feng, Shih-Hung Tsai, Yi-Fan Li, Kun-Hsin Chen, Tong-Jyun Huang, Jyh-Shyang Jenq, Nan-Yuan Huang
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Patent number: 10109531Abstract: A semiconductor structure includes a substrate, a plurality of fin shaped structures, a trench, and a first bump. The substrate has a base, and the fin shaped structures protrude from the base. The trench is recessed from the base of the substrate. The first bump is disposed within the trench and protrudes from a bottom surface of the trench. A topmost portion of the first bump is lower than the base, and a width of the first bump is larger than a width of each of the fin shaped structures.Type: GrantFiled: June 8, 2017Date of Patent: October 23, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Te-Chang Hsu, An-Chi Liu, Nan-Yuan Huang, Yu-Chih Su, Cheng-Pu Chiu, Tien-Shan Hsu, Chih-Yi Wang, Chi-Hsuan Cheng
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Publication number: 20170263732Abstract: A semiconductor device preferably includes a substrate, a fin-shaped structure on the substrate, a buffer layer on the fin-shaped structure, and an epitaxial layer on the buffer layer. Preferably, the buffer layer is made of silicon germanium and including three or more than three elements. The buffer layer also includes dopants selected from the group consisting of P, As, Sb, Bi, C, and F.Type: ApplicationFiled: April 6, 2017Publication date: September 14, 2017Inventors: Li-Wei Feng, Shih-Hung Tsai, Yi-Fan Li, Kun-Hsin Chen, Tong-Jyun Huang, Jyh-Shyang Jenq, Nan-Yuan Huang
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Publication number: 20170179292Abstract: A non-planar transistor is provided. It includes a substrate, a fin structure, a gate structure, a first spacer structure and a source/drain region. The fin structure is disposed on the substrate, the gate structure is disposed on the fin structure. The fin structure includes an upper portion, a concave portion and a lower portion, and the concave portion is disposed between the upper portion and the lower portion. The first spacer structure is disposed on a sidewall of the gate structure. The first spacer structure includes a first spacer and a second spacer, wherein the first spacer is disposed between the second spacer, and a height of the first spacer is different from a height of the second spacer. The source/drain region is disposed in a semiconductor layer at two sides of the first spacer structure.Type: ApplicationFiled: March 2, 2017Publication date: June 22, 2017Inventors: Jhen-Cyuan Li, Nan-Yuan Huang, Shui-Yen Lu
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Patent number: 9653603Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a recess in the substrate; forming a buffer layer in the recess; forming an epitaxial layer on the buffer layer; and removing part of the epitaxial layer, part of the buffer layer, and part of the substrate to form fin-shaped structures.Type: GrantFiled: April 26, 2016Date of Patent: May 16, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Li-Wei Feng, Shih-Hung Tsai, Yi-Fan Li, Kun-Hsin Chen, Tong-Jyun Huang, Jyh-Shyang Jenq, Nan-Yuan Huang
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Patent number: 9627541Abstract: A non-planar transistor is provided. It includes a substrate, a fin structure, a gate structure, a spacer structure and a source/drain region. The fin structure is disposed on the substrate, the gate structure is disposed on the fin structure. The spacer structure is disposed on a sidewall of the gate structure. The spacer structure includes a first spacer with a first height and a second spacer with a second height, wherein the first spacer is disposed between the second spacer, and the first height is different from the second height. The source/drain region is disposed in a semiconductor layer at two sides of the spacer structure. The present invention further provides a method of forming the same.Type: GrantFiled: June 17, 2015Date of Patent: April 18, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Jhen-Cyuan Li, Nan-Yuan Huang, Shui-Yen Lu
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Patent number: 9614034Abstract: The present invention provides a semiconductor structure, including a substrate, having a recess disposed therein, an insulating layer filled in the recess and disposed on a surface of the substrate, and at least one fin structure disposed in the insulating layer, the fin structure consisting of two terminal parts and a central part disposed between two terminal parts. The terminal parts are disposed on the surface of the substrate and directly contact the substrate, and the central part is disposed right above the recess.Type: GrantFiled: October 16, 2015Date of Patent: April 4, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Jhen-Cyuan Li, Nan-Yuan Huang, Shui-Yen Lu
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Publication number: 20170084688Abstract: The present invention provides a semiconductor structure, including a substrate, having a recess disposed therein, an insulating layer filled in the recess and disposed on a surface of the substrate, and at least one fin structure disposed in the insulating layer, the fin structure consisting of two terminal parts and a central part disposed between two terminal parts. The terminal parts are disposed on the surface of the substrate and directly contact the substrate, and the central part is disposed right above the recess.Type: ApplicationFiled: October 16, 2015Publication date: March 23, 2017Inventors: Jhen-Cyuan Li, Nan-Yuan Huang, Shui-Yen Lu
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Patent number: 9583394Abstract: The present invention provides a method for forming a semiconductor structure, comprising: firstly, a substrate is provided, having a first fin structure and a second fin structure disposed thereon, next, a first isolation region is formed between the first fin structure and the second fin structure, a second isolation region is formed opposite the first fin structure from the first isolation region, and at least an epitaxial layer is formed on the side of the first fin structure and the second fin structure, wherein the epitaxial layer has a bottom surface, the bottom surface extending from the first fin structure to the second fin structure, and the bottom surface is lower than a bottom surface of the first isolation region and a top surface of the second isolation region, in addition, the epitaxial layer has a stepped-shaped sidewall profile.Type: GrantFiled: October 14, 2016Date of Patent: February 28, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Li-Wei Feng, Shih-Hung Tsai, Hon-Huei Liu, Chao-Hung Lin, Nan-Yuan Huang, Jyh-Shyang Jenq
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Publication number: 20170033015Abstract: The present invention provides a method for forming a semiconductor structure, comprising: firstly, a substrate is provided, having a first fin structure and a second fin structure disposed thereon, next, a first isolation region is formed between the first fin structure and the second fin structure, a second isolation region is formed opposite the first fin structure from the first isolation region, and at least an epitaxial layer is formed on the side of the first fin structure and the second fin structure, wherein the epitaxial layer has a bottom surface, the bottom surface extending from the first fin structure to the second fin structure, and the bottom surface is lower than a bottom surface of the first isolation region and a top surface of the second isolation region, in addition, the epitaxial layer has a stepped-shaped sidewall profile.Type: ApplicationFiled: October 14, 2016Publication date: February 2, 2017Inventors: Li-Wei Feng, Shih-Hung Tsai, Hon-Huei Liu, Chao-Hung Lin, Nan-Yuan Huang, Jyh-Shyang Jenq