Patents by Inventor Naofumi Nakamura

Naofumi Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6291891
    Abstract: A semiconductor device manufacturing method comprises a step of forming a trench to a first insulation film formed on a semiconductor substrate, and forming a lower level wiring in the trench, a step of forming at least one conductive layer on the semiconductor substrate to coat the lower level wiring, a step of forming at least one thin film layer on the conductive layer, a step of forming a hard mask by patterning the thin film, a step of etching the conductive layer by using the hard mask as an etching mask, and forming a conductive pillar-shaped structure, whose upper surface is covered with the hard mask, on the lower level wiring, a step of forming a second insulation film on the semiconductor substrate so that the pillar-shaped structure is buried, a step of forming a wiring trench in which at least the hard mask is exposed, and a step of burying a conductor into the wiring trench after the hard mask is removed, and forming an upper level wiring in the wiring trench.
    Type: Grant
    Filed: January 12, 1999
    Date of Patent: September 18, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuyuki Higashi, Noriaki Matsunaga, Akihiro Kajita, Tetsuo Matsuda, Tadashi Iijima, Hisashi Kaneko, Hideki Shibata, Naofumi Nakamura, Minakshisundaran Balasubramanian Anand, Tadashi Matsuno, Katsuya Okumura
  • Patent number: 5786604
    Abstract: A diamond semiconductor device having at least one MESFET integrated on a single diamond substrate and insulated from other semiconductor elements is made by preparing a homoepitaxial diamond film 1 having a hydrogen-terminated surface; then making a drain ohmic contact 3, a source ohmic contact 4, both of gold, and a gate electrode 5 of aluminum on the film 1; and changing a site of the hydrogen-terminated surface other than the site for the MESFET to be terminated with atoms other than hydrogen atoms.
    Type: Grant
    Filed: September 13, 1995
    Date of Patent: July 28, 1998
    Assignee: Tokyo Gas Co., Ltd.
    Inventors: Satoshi Yamashita, Hiroshi Kawarada, Masahiro Itoh, Naofumi Nakamura
  • Patent number: 5236522
    Abstract: In an Fe-base alloy, Ni is contained by 28 to 34% by weight and Co by 2 to 7% by weight with an average grain size of 30 .mu.m or less. 60 to 95% of crystal grains are oriented in a range of .+-.5 to 45 degrees deviated from the ideal orientation of {100} [001]. Resultant low thermal expansion of the alloy assures high doming characteristics of a shadow mask made thereof.
    Type: Grant
    Filed: September 25, 1992
    Date of Patent: August 17, 1993
    Assignees: Yamaha Metanix, Mitsubishi Electric Corp., Dainippon Printing Co., Ltd.
    Inventors: Norio Fukuda, Naofumi Nakamura, Atushi Hattori, Hideya Itoh, Akira Makita, Tsutomu Hatano
  • Patent number: 5164021
    Abstract: In composition of a Fe-Ni alloy used for television shadow masks and containing in, Co, Mn, Si and Cr as the major components, additional inclusion of Be assures high deformation resistance and easy pore formation via etching without impairing its inherent low thermal expansion. Introduction of annealing at 800.degree. to 1200.degree. C. temperature into production process sufficiently lowers proof stress of the product without causing any noticeable crystal coarseness. Increased mechanical strength enables production of a thin shadow mask material well suited for pore formation via etching, thereby assuring high grade screen display.
    Type: Grant
    Filed: November 14, 1990
    Date of Patent: November 17, 1992
    Assignee: Yamaha Corporation
    Inventors: Jun Kato, Tsuyuki Watanabe, Naofumi Nakamura