Abstract: A vertical spin transistor according to an embodiment of the present invention includes: a first source/drain layer including a layer formed of magnetic material; a protruding structure including, a channel layer formed on the first source/drain layer and including a layer formed of semiconductor, and a second source/drain layer formed on the channel layer and including a layer formed of magnetic material; a gate insulating film formed on a side of the channel layer; and a gate electrode formed on a surface of the gate insulating film.

Abstract: A semiconductor device includes an insulator layer, and an n-channel MIS transistor having an n channel and a pMIS transistor having a p channel which are formed on the insulator layer, wherein the n channel of the n-channel MIS transistor is formed of an Si layer having a uniaxial tensile strain in a channel length direction, the p channel of the p-channel MIS transistor is formed of an SiGe or Ge layer having a uniaxial compressive strain in the channel length direction, and the channel length direction of each of the n-channel MIS transistor and the p-channel MIS transistor is a <110> direction.

Abstract: In a semiconductor device including a multi-gate MIS transistor having a channel on a plurality of surfaces, a gate electrode is formed on a gate insulating film on side surfaces of an island-like semiconductor layer formed along a given direction on an insulating film, and source/drain electrodes are formed in contact with the semiconductor layer. The semiconductor layer has a plurality of side surfaces along the given direction. All angles formed by adjacent side surfaces are larger than 90°. A section perpendicular to the given direction is vertically and horizontally symmetrical.

Abstract: A method of manufacturing a semiconductor device. In the method, a substrate is prepared, which includes a buried oxide film and a SiGe layer formed on the buried oxide film. Then, heat treatment is performed on the substrate at a temperature equal to or lower than a first temperature, to form a protective oxide film on a surface of the SiGe layer. Next, the substrate having the protective oxide film is heated in a non-oxidizing atmosphere to a second temperature higher than the first temperature. Further, heat treatment is performed on the substrate thus heated, in an oxidizing atmosphere at a temperature equal to or higher than the second temperature, to form oxide the SiGe layer, make the SiGe layer thinner and increasing Ge concentration in the SiGe layer, thus forming a SiGe layer having the increased Ge concentration.

Abstract: A semiconductor device includes an n-channel MIS transistor and a p-channel MIS transistor on a semiconductor layer formed on an insulating layer, in which the channel of the n-channel MIS transistor is formed of a strained Si layer having biaxial tensile strain and the channel of the p-channel MIS transistor is formed of a strained SiGe layer having uniaxial compression strain in the channel length direction.

Abstract: A semiconductor device comprises a base substrate, a silicon oxide layer formed on the base substrate, a first semiconductor layer formed on the silicon oxide layer, the first semiconductor layer including an SiGe layer with a Ge concentration not less than 30 atomic %, a second semiconductor layer formed on the first semiconductor layer, the second semiconductor layer including a Ge layer or an SiGe layer with a Ge concentration higher than the first semiconductor layer, a gate electrode configured to induce a channel in a surface region of the second semiconductor layer, and a gate insulating film formed between the second semiconductor layer and the gate electrode.

Abstract: A semiconductor device includes an insulating layer, a semiconductor board formed on a selected portion of the insulating layer, a semiconductor layer formed on at least one of the major side surfaces of the semiconductor board, which is different from the semiconductor board in lattice constant, and having source and drain regions and a channel region therebetween, the area of the channel region being larger than that of the bottom surface of the semiconductor board, which contacts the insulating layer, and a gate electrode formed on the channel region via a gate insulating layer.

Abstract: An integrated circuit device comprises an insulation layer formed on a substrate, a plurality of lattice relaxed SiGe layers each formed in an island form on the insulation layer, wherein a maximum size of the island form thereof is 10 &mgr;m or less, one of a strained Si layer, a strained SiGe layer and a strained Ge layer formed on at least one of the plurality of lattice relaxed SiGe layers, and a field effect transistor having a gate electrode and source and drain regions, wherein the gate electrode is formed on one of the strained Si layer, the strained SiGe layer and the strained Ge layer with a gate insulation film is disposed therebetween, and the source and drain regions is formed to sandwich a channel region formed below the gate electrode with the gate insulation film disposed therebetween.

Abstract: A semiconductor device comprises a base substrate, a silicon oxide layer formed on the base substrate, a first semiconductor layer formed on the silicon oxide layer, the first semiconductor layer including an SiGe layer with a Ge concentration not less than 30 atomic %, a second semiconductor layer formed on the first semiconductor layer, the second semiconductor layer including a Ge layer or an SiGe layer with a Ge concentration higher than the first semiconductor layer, a gate electrode configured to induce a channel in a surface region of the second semiconductor layer, and a gate insulating film formed between the second semiconductor layer and the gate electrode.

Abstract: A method of manufacturing a semiconductor device which includes forming a first SiGe layer having a low content of Ge, forming an oxide layer by implanting oxygen ions into the first SiGe layer, and then annealing the first SiGe layer. The method also includes forming, on the first SiGe layer, a second SiGe layer which has a higher content of Ge than the first SiGe layer, forming a strained Si layer on the second SiGe layer, and forming a field effect transistor in which the strained Si layer is used a channel region. Further, a field effect transistor may be formed on a semiconductor substrate having an indefectible, high-quality, buried oxide layer and a largely strained Si layer, and hence a high-speed, low-power-consumption semiconductor device can be realized.

Abstract: A semiconductor device includes an insulating layer, a semiconductor board formed on a selected portion of the insulating layer, a semiconductor layer formed on at least one of the major side surfaces of the semiconductor board, which is different from the semiconductor board in lattice constant, and having source and drain regions and a channel region therebetween, the area of the channel region being larger than that of the bottom surface of the semiconductor board, which contacts the insulating layer, and a gate electrode formed on the channel region via a gate insulating layer.

Abstract: A method of manufacturing a semiconductor device which includes forming a first SiGe layer having a low content of Ge, forming an oxide layer by implanting oxygen ions into the first SiGe layer, and then annealing the first SiGe layer. The method also includes forming, on the first SiGe layer, a second SiGe layer which has a higher content of Ge than the first SiGe layer, forming a strained Si layer on the second SiGe layer, and forming a field effect transistor in which the strained Si layer is used a channel region. Further, a field effect transistor may be formed on a semiconductor substrate having an indefectible, high-quality, buried oxide layer and a largely strained Si layer, and hence a high-speed, low-power-consumption semiconductor device can be realized.

Abstract: A semiconductor device comprises a base substrate, a silicon oxide layer formed on the base substrate, a first semiconductor layer formed on the silicon oxide layer, the first semiconductor layer including an SiGe layer with a Ge concentration not less than 30 atomic %, a second semiconductor layer formed on the first semiconductor layer, the second semiconductor layer including a Ge layer or an SiGe layer with a Ge concentration higher than the first semiconductor layer, a gate electrode configured to induce a channel in a surface region of the second semiconductor layer, and a gate insulating film formed between the second semiconductor layer and the gate electrode.

Abstract: A method of manufacturing a semiconductor device which includes forming a first SiGe layer having a low content of Ge, forming an oxide layer by implanting oxygen ions into the first SiGe layer, and then annealing the first SiGe layer. The method also includes forming, on the first SiGe layer, a second SiGe layer which has a higher content of Ge than the first SiGe layer, forming a strained Si layer on the second SiGe layer, and forming a field effect transistor in which the strained Si layer is used a channel region. Further, a field effect transistor may be formed on a semiconductor substrate having an indefectible, high-quality, buried oxide layer and a largely strained Si layer, and hence a high-speed, low-power-consumption semiconductor device can be realized.

Abstract: High-speed and low-power-consuming transistors such as field effect transistors having strained Si channels and hetero-bipolar transistors are integrated with each other. Used here is a complex structure in which an MOSFET having a thin-film SiGe buffer layer and a strained Si channel are laminated on an insulating film and an HBT having an SiGe base layer formed on a thin-film SiGe layer by epitaxial growth and an Si emitter layer formed on the SiGe base layer are combined with each other. The thin-film SiGe layer formed on the insulating film of the MOSFET is made thinner than the counterpart of the HBT. The thin-film SiGe layer formed on the insulating film of the MOSFET has Ge concentration higher than that of the counterpart of the HBT.

Abstract: A method of manufacturing a semiconductor device comprising the steps of forming a first crystal silicon layer doped with oxygen on a single crystal silicon substrate, forming a crystal silicon-germanium layer on the first crystal silicon layer, forming a second crystal silicon layer on the crystal silicon-germanium layer, and imparting strain to the second crystal silicon layer by a thermal treatment.

Abstract: High-speed and low-power-consuming transistors such as field effect transistors having strained Si channels and hetero-bipolar transistors are integrated with each other. Used here is a complex structure in which an MOSFET having a thin-film SiGe buffer layer and a strained Si channel are laminated on an insulating film and an HBT having an SiGe base layer formed on a thin-film SiGe layer by epitaxial growth and an Si emitter layer formed on the SiGe base layer are combined with each other. The thin-film SiGe layer formed on the insulating film of the MOSFET is made thinner than the counterpart of the HBT. The thin-film SiGe layer formed on the insulating film of the MOSFET has Ge concentration higher than that of the counterpart of the HBT.

Abstract: A method of manufacturing a semiconductor device which includes forming a first SiGe layer having a low content of Ge, forming an oxide layer by implanting oxygen ions into the first SiGe layer, and then annealing the first SiGe layer. The method also includes forming, on the first SiGe layer, a second SiGe layer which has a higher content of Ge than the first SiGe layer, forming a strained Si layer on the second SiGe layer, and forming a field effect transistor in which the strained Si layer is used a channel region. Further, a field effect transistor may be formed on a semiconductor substrate having an indefectible, high-quality, buried oxide layer and a largely strained Si layer, and hence a high-speed, low-power-consumption semiconductor device can be realized.

Abstract: The invention is intended to form, on an insulating layer, a thin SiGe layer serving as an underlying layer for obtaining a strained silicon layer, and to provide a satisfactory strained Si layer. A SiGe layer 13 is formed on a Si substrate 11 and an oxygen ion implantation is effected with ensuring the detainment within the layer thickness of the SiGe layer 13. The SiGe layer 13 is lattice-relaxed by a heat treatment and a buried insulating layer 15 is formed simultaneously in the SiGe layer 13. A strained Si layer 17 is re-grown on the lattice-relaxed SiGe layer 13.

Abstract: A semiconductor device includes a superlattice having a first semiconductor layer having a first band-gap, a second semiconductor layer having a band-gap narrower than the first band-gap, the superlattice having a band structure with an energy level of a conduction band of the second semiconductor layer being lower than an energy level of a conduction band of the first semiconductor layer and an energy level of a valence band of the second semiconductor layer being lower than an energy level of a valence band of the first semiconductor layer, or a band structure with an energy level of a conduction band of the second semiconductor layer being higher than an energy level of a conduction band of the first semiconductor layer and an energy level of a valence band of the second semiconductor layer being lower than an energy level of a valence band of the first semiconductor layer, an exposed face formed on a plane different from a plane orientation on which the superlattice is formed, an end face of the superlatt