Abstract: A mechanism of making a low standby current caused by power off compatible with a fast return operation from a standby caused by an interrupt is realized. An information processing device has a first area that includes a central processing unit and peripheral circuit modules, a second area having information holding circuits for holding values of registers contained in the peripheral circuit modules, and a first power switch for controlling supply of a current to the first area. When the information processing device operates in a first mode, an operating current is supplied to the first area and the second area. When the information processing device operates in a second mode, the first power switch is controlled so that the supply of the current to the first area can be shut off, and the supply of the current to the second area is continued.

Abstract: In a processor system comprising of a processor having an instruction decoder 22, a general register 61 composed of a plurality of register areas and at least one ALU 60, and a Java accelerator 30 for converting a Java bytecode sequence to a native instruction sequence for the processor and supplying the native instruction sequence to the instruction decoder. The Java accelerator 30 is composed of a bytecode translator 40 for converting the Java bytecode sequence to the native instruction sequence for the processor and a register status control unit 50 for mapping a Java operand stack to any of the register areas of the general register and detecting a bytecode redundant for the processor. When a redundant bytecode is detected by the register status control unit 50, the supply of the native instruction from the bytecode translator 40 to the instruction decoder 22 is inhibited.

Abstract: A branch control memory store branch instructions which are adapted for optimizing performance of programs run on electronic processors. Flexible instruction parameter fields permit a variety of new branch control and branch instruction implementations best suited for a particular computing environment. These instructions also have separate prediction bits, which are used to optimize loading of target instruction buffers in advance of program execution, so that a pipeline within the processor achieves superior performance during actual program execution.

Abstract: A processor is disclosed utilizing improved branch control and branch instructions for optimizing performance of programs run on such processors. Flexible instruction parameter fields permit a variety of new branch control and branch instruction implementations best suited for a particular computing environment. These instructions also have separate prediction bits, which are used to optize loading of target instruction buffers in advance of program execution, so that a pipeline within the processor achieves superior performance during actual program execution.

Abstract: In a multi-processor system interconnecting processor units, memory units, and input/output units connected to input/output devices via a crossbar switch having a plurality of ports, the transmitter of each processor unit has a circuit for determining a destination of an access request in the following manner. For an access request to a main memory, the access request is transferred to all processor units and one memory unit storing the data to be accessed. For an access request to a memory mapped register of the input/output device, the access request is broadcast to all input/output units. For an access request to a memory mapped register belonging to any one of the processor units, memory units, and input/output units, the access request is broadcast to all units via the crossbar switch.

Abstract: A method and apparatus are provided for event detection for a multiple instruction-set processor. In one example of the apparatus, a data processing device comprises an instruction execution device configured to execute a first instruction set as specific instructions; an instruction conversion circuit configured to convert instructions of a second instruction set into a first instruction string of the first instruction set, and further configured to supply the first instruction string to the instruction execution device; and a counter device configured to count a prescribed event, wherein the instruction conversion circuit is further configured to output a prescribed instruction when the counter device is satisfied by a prescribed condition.

Abstract: Disclosed here is a mechanism provided in an instruction translator for translating an intermediate code (Java bytecode) to an instruction string so as to be interpreted by an instruction execution block corresponding to various upgraded versions of a virtual machine (computer) (VM). Each instruction included in the first instruction group of the intermediate code is translated to an instruction to be interpreted by hardware while each instruction included in the second instruction group is translated by software. The information processing device is configured so that the intermediate code has a storage area for storing information for denoting which of the first and second instruction groups includes the intermediate code. Thus, instruction translation can be made by the same hardware to cope with various upgraded versions of a VM if the values are set in the setting register. In addition, the hardware is not required to be modified to translate instructions even when the VM version is upgraded.

Abstract: Multiprocessor system, having a translation lookaside buffer (TLB) in each processor, and having a structure for avoiding TLB purge overhead. Each processor node is provided with a partial main memory and a physical page map table (PPT). The PPT stores mapping between physical page number of main memory and virtual page number. Every memory access transaction for other node specifies physical address and virtual page number. Instead of strictly maintaining TLB coherency by broadcasting TLB purge transaction, an access destination node checks the coincidence between the virtual page number specified in the memory access transaction and the virtual page number mapped in the PPT when the transaction is received. If both are coincident, the memory access is executed. If not coincident, an error message is transferred to an access requesting source.

Abstract: The present invention provides a hardware accelerator, which allows faster switching between processing modes. In an information processing device with a bytecode accelerator BCA for translating a stack-based intermediate code (bytecode) into register-based instructions, a selector SEL for switching between BCA and soft VM is posed between an instruction part FET and a decode part DEC and data transfer paths P4 and P5 are formed between BCA and the register file REG_FILE. When bytecode accelerator BCA is activated, the P3 side is selected by the selector SEL and the translated CPU instructions are transferred to the decode part DEC. If the intermediate language code cannot be translated by the BCA, the processing mode is switched to software processing. During switching between the modes, internal information of BCA can be transferred between BCA and REG_FILE in parallel, achieving faster mode switching.

Abstract: When a leakage current of a circuit block under a non-use state is reduced by means of a power switch, frequent ON/OFF operations of the switch within a short time invite an increase of consumed power, on the contrary. Because a pre-heating time is necessary from turn-on of the switch till the circuit block becomes usable, control of the switch during an operation deteriorates a processing time of a semiconductor device. The switch is ON/OFF-controlled with a task duration time of a CPU core for controlling logic circuits and memory cores as a unit. After the switch is turned off, the switch is again turned on before termination of the task in consideration of the pre-heating time.

Abstract: A system is provided for improving the performance of multimedia computer operations. It includes a streaming data cache memory, a bus, a processor coupled to the bus, and an interface circuit coupled to the bus and to an external source of information, for example, a high speed communications link. The streaming data cache is coupled to a memory controller, and receives data only from the external source of information. After data in the streaming data cache memory is accessed the first time, the data is invalidated and not used again.

Abstract: A semiconductor device and the operation control method thereof are provided, which realize a highly generalized frequency control mechanism so as to allow a microprocessor to operate in lower power consumption, but with higher performance, without depending on the OS.

Abstract: A processor element, structured to execute a 32-bit fixed length instruction set architecture, is backward compatible for executing a 16-bit fixed length instruction set architecture by translating each of the 16-bit instructions into a sequence of one or more 32-bit instructions. The 32-bit instruction set architecture includes “prepare to branch” instructions that allow target addresses for branch instructions to be set up in advance of the branch. The 32-bit prepare to branch and branch instructions are combined to execute a 16-bit branch instruction coupled with a 16-bit Delay Slot instruction.

Abstract: A processor having an execution pipeline and a cache memory including a plurality of cache blocks with instruction words held in selected ones of the cache blocks. An ICBI address buffer is provided for holding addresses of instruction cache blocks to be invalidated by ICBI instructions pending in the processor's execution pipeline. An instruction cache controller coupled to the cache memory generates cache accesses to invalidate specified cache blocks in response to receiving buffered addresses from the ICBI address buffer. Preferably the cache accesses serve to commit ICBI instructions to the instruction cache asynchronously with respect to the processor's execution pipeline.

Abstract: An improved preload/prefetching architecture is disclosed for controlling branch target instruction loading in a pipelined processor. Branch target instructions can be speculatively preloaded/prefetched based on a first prediction indicator provided in a branch control instruction, and they also can be actually loaded/fetched based on a second prediction indicator provided in a branch instruction. This mechanism results in reduced cache latency during program execution. The preloading/prefetching of branch target instructions can also be prioritized under software control to optimize instruction execution, based on particular indicators specified for branch target instructions within a branch hint buffer.

Abstract: In a bus or switch coupled system having a plurality of processor modules and a memory module, the memory module is provided with a unit for returning a write completion acknowledgement (WRITE_ACK) to a write requesting processor module. If a processor module PM1 is under execution of write-back of a cache line upon arrival of a cache coherence check (CCC) issued from a processor module with a cache miss of the cache line, an “INVALID” signal is returned to the CCC issued processor module PMO after a write completion acknowledgment from the memory module is confirmed and the cache line is invalidated. After confirming the “INVALID” signals from other processor modules, the CCC issued processor module issues a READ transaction to the memory module to obtain correct latest data reflecting the write-back data of the processor module.

Abstract: A cache status report sum up for use in a multiprocessor system having a plurality of processor units each having a processor and a cache memory and a plurality of memory units. The cache status report sum up apparatus sums up cache coherency check results indicating statuses of the cache memories without limiting the number of memory access requests requiring cache coherency checks that can be overlapped when the memory access requests requiring cache coherency checks are executed in an overlapping manner. The cache status report sum up apparatus is provided between the processor units and the memory units and sums up cache coherency check results sent by cache status reporting apparatus included in each processor unit. The cache status reporting apparatus responds to a memory access request requiring a cache coherency check.

Abstract: Information indicative of whether each processor unit caches data which belongs to each of the plural areas of the main memory larger than a cache line is stored in the multicast table. The destinations of a coherent processing request which should be sent to other processor units are limited by the information stored in this table. The interconnection network broadcasts the request to the limited destinations. When the processor unit of the destination of this processing request sends back a cache status of the data designated by the request, it also sends back the caching status in the processor unit concerning a specific memory area which includes the data. Depending on this send back, the request source processor unit renews a portion relating to the destination processor unit within the caching status concerning that specific memory area stored in the processor unit.

Abstract: In a multi-processor system interconnecting processor units, memory units, and input/output units connected to input/output devices via a crossbar switch having a plurality of ports, the transmitter of each processor unit has a circuit for determining a destination of an access request in the following manner. For an access request to a main memory, the access request is transferred to all processor units and one memory unit storing the data to be accessed. For an access request to a memory mapped register of the input/output device, the access request is broadcast to all input/output units. For an access request to a memory mapped register belonging to any one of the processor units, memory units, and input/output units, the access request is broadcast to all units via the crossbar switch.

Abstract: To improve the function of a circuit for prefetching data accessed by a processor, a prefetch unit incorporates therein a circuit for issuing a request to read out one group of data to be prefetched and registers for holding the group of data read in response to the read request therein. The group of data are read out from a cache memory or a main memory under the control of a cache request unit. A plurality of groups of data can be prefetched. When data designation is made, the processor requests the cache memory to read a block to which the data to be prefetched belongs. A circuit is also included in the prefetch unit, wherein when prefetched data is subsequently updated by the processor, its updated data is made invalid. Elements of a vector complex in structure, such as an indexed vector or the like can be also read out. It is also possible to cope with an interrupt generated within the processor.