Abstract: An auxiliary data processor having an built-in multi-entry data memory is directly connected to a main storage, and executes, directly accessing the main storage, commands sent from a plurality of instruction processors. One data memory entry is assigned to an instruction processor that issued a command, and reserves data fetched from the main storage in response to the command so that the next command can use part of that data. A tag circuit holds an identifier of each instruction processor to which a data memory entry has been assigned and the address and length of data hold in that entry, and see that each command uses the reserved data correctly. Each instruction processor selects commands to be sent to the auxiliary data processor depending upon the conditions of operands. A large amount of data is processed at a high rate, minimizing cache pollution.