Patents by Inventor Naoki Esaka

Naoki Esaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11543997
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller acquires, from a host, write data having the same first size as a data write unit of the nonvolatile memory and obtained by dividing write data associated with one write command having a first identifier indicating a first write destination block in a plurality of write destination blocks into a plurality of write data or combining write data associated with two or more write commands having the first identifier. The controller writes the acquired write data having the first size to the first write destination block by a first write operation.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: January 3, 2023
    Assignee: Kioxia Corporation
    Inventors: Shinichi Kanno, Hideki Yoshida, Naoki Esaka, Hiroshi Nishimura
  • Publication number: 20220404966
    Abstract: According to one embodiment, a controller constructs a plurality of block groups. The plurality of block groups include at least a first block group configured using a first type block group and a second block group configured using a second block group. The first type block group includes a plurality of non-defective blocks obtained by selecting one or more non-defective blocks in an equal number from each of a plurality of dies or each of a plurality of planes. The second type block group includes a plurality of non-defective blocks. The number of non-defective blocks included in the second type block group is equal to the number of non-defective blocks included in the first type block.
    Type: Application
    Filed: March 3, 2022
    Publication date: December 22, 2022
    Applicant: Kioxia Corporation
    Inventors: Shinichi KANNO, Naoki ESAKA
  • Publication number: 20220350530
    Abstract: A controller manages a plurality of block groups each including one or more blocks among a plurality of blocks provided in a non-volatile memory. The controller assigns one of the plurality of block groups to each of plurality of zones. The controller writes write data which is to be written to a first zone to a shared write buffer and writes write data which is to be written to a second zone to the shared write buffer. When a total size of the write data in the first zone stored in the shared write buffer reaches a capacity of the first zone, the controller copies the write data in the first zone stored in the shared write buffer to the first block group assigned to the first zone.
    Type: Application
    Filed: March 2, 2022
    Publication date: November 3, 2022
    Applicant: Kioxia Corporation
    Inventors: Hideki YOSHIDA, Shinichi KANNO, Naoki ESAKA
  • Publication number: 20220300182
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller receives a first write request associated with first data from a host. In response to a lapse of first time since the reception of the first write request, the controller starts a write process of second data to the nonvolatile memory. The second data includes at least the first data. The controller transmits a first response to the first write request to the host in response to completion of the write process. The first time is time obtained by subtracting second time from third time designated by the host as a time limit of the transmission of the first response since the reception of the first write request.
    Type: Application
    Filed: September 7, 2021
    Publication date: September 22, 2022
    Applicant: Kioxia Corporation
    Inventors: Naoki ESAKA, Shinichi KANNO
  • Publication number: 20220236916
    Abstract: According to one embodiment, in response to receiving a first namespace create command specifying a first attribution from a host, a controller creates a first namespace having the first attribution and a first logical address range. The first logical address range includes logical addresses. The controller sets each of the logical addresses to an unallocated state in which a physical address of the nonvolatile memory is not mapped, during a first period from a time when receiving a power loss advance notification or when detecting an unexpected power loss until a time when the controller becomes a ready state by resupply of a power to the memory system.
    Type: Application
    Filed: September 13, 2021
    Publication date: July 28, 2022
    Inventors: Naoki ESAKA, Shinichi KANNO
  • Publication number: 20220214966
    Abstract: According to one embodiment, a controller of a memory system writes write data associated with a set of received write requests to a first write destination storage region in a first write mode of writing a plurality of bits per memory cell, without writing the write data to a second storage region. When receiving from a host a first request to cause a state of the first write destination storage region to transition to a second state in which writing is suspended, the controller transfers un-transferred remaining write data from a write buffer of the host to an internal buffer, and writes the remaining write data to the second storage region in a second write mode of writing 1 bit per memory cell.
    Type: Application
    Filed: March 21, 2022
    Publication date: July 7, 2022
    Applicant: Kioxia Corporation
    Inventors: Shinichi KANNO, Naoki ESAKA
  • Publication number: 20220188005
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller manages at least one storage area that is obtained by logically dividing a storage space of the nonvolatile memory. One or more storage areas in the at least one storage area store one or more data pieces, respectively. The controller manages first information on one or more times in which integrity of the one or more data pieces have been confirmed last, respectively.
    Type: Application
    Filed: September 8, 2021
    Publication date: June 16, 2022
    Applicant: Kioxia Corporation
    Inventor: Naoki ESAKA
  • Patent number: 11321231
    Abstract: According to one embodiment, a controller of a memory system writes write data associated with a set of received write requests to a first write destination storage region in a first write mode of writing a plurality of bits per memory cell, without writing the write data to a second storage region. When receiving from a host a first request to cause a state of the first write destination storage region to transition to a second state in which writing is suspended, the controller transfers un-transferred remaining write data from a write buffer of the host to an internal buffer, and writes the remaining write data to the second storage region in a second write mode of writing 1 bit per memory cell.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: May 3, 2022
    Assignee: Kioxia Corporation
    Inventors: Shinichi Kanno, Naoki Esaka
  • Publication number: 20220083466
    Abstract: According to one embodiment, a memory system manages a plurality of management tables corresponding to a plurality of first blocks in a nonvolatile memory. Each management table includes a plurality of reference counts corresponding to a plurality of data in a corresponding first block. The memory system copies a set of data included in a copy-source block for garbage collection and corresponding respectively to reference counts belonging to a first reference count range to a first copy-destination block, and copies a set of data included in the copy-source block and corresponding respectively to reference counts belonging to a second reference count range having a lower limit higher than an upper limit of the first reference count range to a second copy-destination block.
    Type: Application
    Filed: September 1, 2021
    Publication date: March 17, 2022
    Inventors: Shinichi Kanno, Naoki Esaka
  • Publication number: 20220083234
    Abstract: According to one embodiment, a controller of a memory system performs a first operation a plurality of times for each of a plurality of first blocks. The first operation includes a write operation for writing data in a first write mode for writing m-bit data per memory cell and a data erase operation. While a second block is not a defective block, the controller performs a second operation a plurality of times for the second block. The second operation includes a write operation for writing data in a second write mode for writing n-bit data per memory cell and a data erase operation. When the second block is a defective block, the controller selects a first block from the plurality of first blocks, and writes second write data to the selected first block in the second write mode.
    Type: Application
    Filed: November 29, 2021
    Publication date: March 17, 2022
    Applicant: Kioxia Corporation
    Inventors: Naoki ESAKA, Shinichi KANNO
  • Publication number: 20220066693
    Abstract: According to one embodiment, a memory system receives from a host a first write request including a first block identifier designating a first write destination block to which first write data is to be written. The memory system acquires the first write data from a write buffer temporarily holding write data corresponding to each of the write requests, and writes the first write data to a write destination page in the first write destination block. The memory system releases a region in the write buffer, storing data which is made readable from the first write destination block by writ the first write data to the write destination page. The data made readable is a data of a page in the first write destination block preceding the write destination page.
    Type: Application
    Filed: November 10, 2021
    Publication date: March 3, 2022
    Applicant: Toshiba Memory Corporation
    Inventors: Shinichi KANNO, Hideki YOSHIDA, Naoki ESAKA
  • Patent number: 11237756
    Abstract: According to one embodiment, a memory system receives from a host a first write request including a first block identifier designating a first write destination block to which first write data is to be written. The memory system acquires the first write data from a write buffer temporarily holding write data corresponding to each of the write requests, and writes the first write data to a write destination page in the first write destination block. The memory system releases a region in the write buffer, storing data which is made readable from the first write destination block by writing the first write data to the write destination page. The data made readable is a data of a page in the first write destination block preceding the write destination page.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: February 1, 2022
    Assignee: Toshiba Memory Coiporation
    Inventors: Shinichi Kanno, Hideki Yoshida, Naoki Esaka
  • Patent number: 11216188
    Abstract: According to one embodiment, a controller of a memory system performs a first operation a plurality of times for each of a plurality of first blocks. The first operation includes a write operation for writing data in a first write mode for writing m-bit data per memory cell and a data erase operation. While a second block is not a defective block, the controller performs a second operation a plurality of times for the second block. The second operation includes a write operation for writing data in a second write mode for writing n-bit data per memory cell and a data erase operation. When the second block is a defective block, the controller selects a first block from the plurality of first blocks, and writes second write data to the selected first block in the second write mode.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: January 4, 2022
    Assignee: Kioxia Corporation
    Inventors: Naoki Esaka, Shinichi Kanno
  • Publication number: 20210382648
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller acquires, from a host, write data having the same first size as a data write unit of the nonvolatile memory and obtained by dividing write data associated with one write command having a first identifier indicating a first write destination block in a plurality of write destination blocks into a plurality of write data or combining write data associated with two or more write commands having the first identifier. The controller writes the acquired write data having the first size to the first write destination block by a first write operation.
    Type: Application
    Filed: August 19, 2021
    Publication date: December 9, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Shinichi KANNO, Hideki YOSHIDA, Naoki ESAKA, Hiroshi NISHIMURA
  • Patent number: 11150835
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller acquires, from a host, write data having the same first size as a data write unit of the nonvolatile memory and obtained by dividing write data associated with one write command having a first identifier indicating a first write destination block in a plurality of write destination blocks into a plurality of write data or combining write data associated with two or more write commands having the first identifier. The controller writes the acquired write data having the first size to the first write destination block by a first write operation.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: October 19, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinichi Kanno, Hideki Yoshida, Naoki Esaka, Hiroshi Nishimura
  • Patent number: 11132295
    Abstract: According to one embodiment, a memory system manages a plurality of management tables corresponding to a plurality of first blocks in a nonvolatile memory. Each management table includes a plurality of reference counts corresponding to a plurality of data in a corresponding first block. The memory system copies a set of data included in a copy-source block for garbage collection and corresponding respectively to reference counts belonging to a first reference count range to a first copy-destination block, and copies a set of data included in the copy-source block and corresponding respectively to reference counts belonging to a second reference count range having a lower limit higher than an upper limit of the first reference count range to a second copy-destination block.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: September 28, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Shinichi Kanno, Naoki Esaka
  • Publication number: 20210223962
    Abstract: According to one embodiment, a controller of a memory system performs a first operation a plurality of times for each of a plurality of first blocks. The first operation includes a write operation for writing data in a first write mode for writing m-bit data per memory cell and a data erase operation. While a second block is not a defective block, the controller performs a second operation a plurality of times for the second block. The second operation includes a write operation for writing data in a second write mode for writing n-bit data per memory cell and a data erase operation. When the second block is a defective block, the controller selects a first block from the plurality of first blocks, and writes second write data to the selected first block in the second write mode.
    Type: Application
    Filed: September 14, 2020
    Publication date: July 22, 2021
    Applicant: Kioxia Corporation
    Inventors: Naoki ESAKA, Shinichi KANNO
  • Publication number: 20210149797
    Abstract: According to one embodiment, a controller of a memory system writes write data associated with a set of received write requests to a first write destination storage region in a first write mode of writing a plurality of bits per memory cell, without writing the write data to a second storage region. When receiving from a host a first request to cause a state of the first write destination storage region to transition to a second state in which writing is suspended, the controller transfers un-transferred remaining write data from a write buffer of the host to an internal buffer, and writes the remaining write data to the second storage region in a second write mode of writing 1 bit per memory cell.
    Type: Application
    Filed: September 10, 2020
    Publication date: May 20, 2021
    Applicant: Kioxia Corporation
    Inventors: Shinichi Kanno, Naoki Esaka
  • Publication number: 20200341681
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller acquires, from a host, write data having the same first size as a data write unit of the nonvolatile memory and obtained by dividing write data associated with one write command having a first identifier indicating a first write destination block in a plurality of write destination blocks into a plurality of write data or combining write data associated with two or more write commands having the first identifier. The controller writes the acquired write data having the first size to the first write destination block by a first write operation.
    Type: Application
    Filed: July 14, 2020
    Publication date: October 29, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Shinichi KANNO, Hideki Yoshida, Naoki Esaka, Hiroshi Nishimura
  • Patent number: 10761771
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller acquires, from a host, write data having the same first size as a data write unit of the nonvolatile memory and obtained by dividing write data associated with one write command having a first identifier indicating a first write destination block in a plurality of write destination blocks into a plurality of write data or combining write data associated with two or more write commands having the first identifier. The controller writes the acquired write data having the first size to the first write destination block by a first write operation.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: September 1, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinichi Kanno, Hideki Yoshida, Naoki Esaka, Hiroshi Nishimura