Patents by Inventor Naoki Kimura

Naoki Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210166451
    Abstract: The appropriateness of a motion of a motion actor who makes a motion in response to a motion of at least one moving body other than him/herself is visualized. To display motion information of a motion actor who makes a motion in response to a motion of at least one moving body other than him/herself, an image showing one sequence which is visible or a plurality of sequences which are visible is output. In this case, a relative time which is a position on a relative time axis corresponds to a position on a specific axis of the image. The one sequence or each of the plurality of sequences graphically shows at least a position on the axis which corresponds to a moving body time that is a relative time at which at least one predetermined motion of the moving body was made, and a position on the axis which corresponds to a motion actor time that is a relative time at which at least one predetermined motion of the motion actor was made.
    Type: Application
    Filed: February 14, 2019
    Publication date: June 3, 2021
    Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Makio KASHINO, Naoki SAIJO, Toshitaka KIMURA, Daiki NASU
  • Patent number: 11013482
    Abstract: A phase contrast X-ray imaging system includes an X-ray source; a plurality of gratings; a detector; a grating movement mechanism; and an image processor that generates a phase contrast image. The image processor generates the phase contrast image by using a pitch of an intensity change and a function which has the pitch as a variable and expresses the intensity change in a pixel value as a grating moves.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: May 25, 2021
    Assignee: Shimadzu Corporation
    Inventors: Naoki Morimoto, Kenji Kimura, Taro Shirai, Takahiro Doki, Satoshi Sano, Akira Horiba
  • Publication number: 20210152272
    Abstract: [Object] Provided is a mechanism for enhancing resistance against an interference that possibly occur due to non-orthogonality of a resource in a communication system holding communication with a mixture of a plurality of communication parameter sets. [Solving Means] A transmitting apparatus holding communication using a plurality of communication parameter sets in a unit resource, and including a processing section that transmits a data signal and a reference signal generated using the parameter sets different between the data signal and the reference signal to a receiving apparatus.
    Type: Application
    Filed: March 14, 2018
    Publication date: May 20, 2021
    Inventors: RYOTA KIMURA, HIROKI MATSUDA, NAOKI KUSASHIMA, YIFU TANG, YUKITOSHI SANADA
  • Publication number: 20210148839
    Abstract: This X-ray phase image capturing system (100) includes an X-ray source (1), a plurality of gratings, and a detector (4), a moving mechanism (8), and an image processing unit (5). The image processing unit (5) is configured to generate a phase-contrast image (15) based on a plurality of feature quantities (12) and feature quantities 14 extracted from a plurality of X-ray image sets (R) acquired by performing fringe scanning a plurality of times in a short time.
    Type: Application
    Filed: November 27, 2018
    Publication date: May 20, 2021
    Inventors: Satoshi SANO, Kenji KIMURA, Taro SHIRAI, Masanobu SATO, Takahiro DOKI, Akira HORIBA, Naoki MORIMOTO
  • Publication number: 20210114131
    Abstract: A welding control device includes an actual position determination part configured to determine an actual position of the position control target on the basis of a weld characteristic amount detected from a captured image captured so as to include at least the position control target, the welding characteristic amount including at least one of a wire position of the weld wire or an electrode position of the electrode; a target position determination part configured to determine a target position being a target of the actual position corresponding to a weld condition for welding the weld target; and a position control part configured to execute a position control of the position control target to bring the actual position to the target position.
    Type: Application
    Filed: March 25, 2019
    Publication date: April 22, 2021
    Applicant: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Yusuke Hazui, Koki Tateishi, Naoki Suda, Kazuhiko Kamo, Masahiro Kimura, Yusuke Sano, Yasushi Nishijima
  • Publication number: 20210054076
    Abstract: The present inventors discovered novel multispecific antigen-binding molecules with excellent cellular cytotoxicity and high stability, which comprise a first domain comprising a first antibody variable region that binds to Claudin 6, a second domain comprising a second antibody variable region that binds to T cell receptor complex. Since the molecules of the present invention show a strong cytotoxicity against cells and tissues expressing Claudin 6, it is possible to produce novel pharmaceutical compositions comprising the multispecific antigen-binding molecules for treating or preventing various cancers.
    Type: Application
    Filed: January 4, 2019
    Publication date: February 25, 2021
    Inventor: Naoki KIMURA
  • Publication number: 20210043235
    Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.
    Type: Application
    Filed: October 22, 2020
    Publication date: February 11, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Masato SUGITA, Naoki Kimura, Daisuke Kimura
  • Patent number: 10847190
    Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: November 24, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Masato Sugita, Naoki Kimura, Daisuke Kimura
  • Publication number: 20200301617
    Abstract: According to one embodiment, a storage device is disclosed. The storage device includes a substrate, a first connector provided on the substrate and including a notch, and a nonvolatile memory provided on the substrate. The storage device further includes a first conductive part provided on the first connector and being adjacent to the notch.
    Type: Application
    Filed: September 11, 2019
    Publication date: September 24, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Naoki KIMURA
  • Publication number: 20200194414
    Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
    Type: Application
    Filed: February 25, 2020
    Publication date: June 18, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Hayato MASUBUCHI, Naoki KIMURA, Manabu MATSUMOTO, Toyota MORIMOTO
  • Patent number: 10656692
    Abstract: According to one embodiment, a memory system includes a volatile memory, a power supply circuit, and a controller. The power supply circuit includes a first power supply path in which power supplied from a host device is supplied to the volatile memory, a second power supply path in which the power is supplied from the internal power supply to the volatile memory, and a switching device that switches between the first power supply path and the second power supply path. In response to an instruction for a transition to a low power consumption mode received from the host device, the controller outputs, to the switching device, an instruction to switch the power supply circuit from the first power supply path to the second power supply path.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: May 19, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Naoki Kimura
  • Publication number: 20200143848
    Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.
    Type: Application
    Filed: January 8, 2020
    Publication date: May 7, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Masato SUGITA, Naoki KIMURA, Daisuke KIMURA
  • Patent number: 10607979
    Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: March 31, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Hayato Masubuchi, Naoki Kimura, Manabu Matsumoto, Toyota Morimoto
  • Patent number: 10593617
    Abstract: According to one embodiment, a semiconductor device includes a first board including a plurality of terminals, a semiconductor chip flip-chip mounted to the first board, and an insulating layer covering the first board and the semiconductor chip. The plurality of terminals include at least one first terminal electrically connected to the semiconductor chip, and at least one second terminal that is not connected to the semiconductor chip, wherein the at least one second terminal is not covered by the insulating layer.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: March 17, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroshi Ashikaga, Naoki Kimura
  • Patent number: 10566033
    Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: February 18, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Masato Sugita, Naoki Kimura, Daisuke Kimura
  • Patent number: 10541382
    Abstract: Provided is an electroluminescent device that emits light of a single color and includes a plurality of functional layers, in which an absorption peak is included in the emission wavelength and at least one absorption peak is included in a complementary color region of an emission wavelength in the range of 380 nm to 780 nm, an absolute value of a deviation (?uv) of a color coordinate of front reflected light at the time of white color illumination from a blackbody locus is below 0.02, and a refractive index and a film thickness of each of the plurality of functional layers are determined to satisfy the formula D(?)?D(0)cos ? (0????D?60 degrees) when an angle dependence of emission intensity is defined as D(?).
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: January 21, 2020
    Assignee: KONICA MINOLTA, INC.
    Inventors: Kou Osawa, Koujirou Sekine, Naoki Kimura
  • Publication number: 20190326275
    Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
    Type: Application
    Filed: July 3, 2019
    Publication date: October 24, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Hayato MASUBUCHI, Naoki KIMURA, Manabu MATSUMOTO, Toyota MORIMOTO
  • Publication number: 20190295664
    Abstract: A memory system includes a connector through which power for the memory system is to be supplied from an external device, a controller, a nonvolatile memory device, a power source circuit connected to the controller and the nonvolatile memory device by power lines through which power is supplied to the controller and the nonvolatile memory device, and a power source control circuit that receives a supply of power from the external device through the connector and supplies the power to the power control circuit. The power source control circuit is configured to detect using a divided voltage of a voltage of the power supplied thereto, that the voltage of the power supplied thereto is higher than a predetermined voltage and interrupt the power supplied to the power control circuit if the voltage of the power supplied thereto is higher than the predetermined voltage.
    Type: Application
    Filed: August 27, 2018
    Publication date: September 26, 2019
    Inventor: Naoki KIMURA
  • Publication number: 20190279686
    Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.
    Type: Application
    Filed: May 28, 2019
    Publication date: September 12, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Masato Sugita, Naoki Kimura, Daisuke Kimura
  • Patent number: 10388640
    Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: August 20, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hayato Masubuchi, Naoki Kimura, Manabu Matsumoto, Toyota Morimoto