Patents by Inventor Naoki Kimura

Naoki Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180358611
    Abstract: Provided is a secondary cell excellent in cycle characteristics. The secondary cell includes a positive electrode 5, a negative electrode 6, and an electrolytic solution. A positive electrode mixture of the positive electrode 5 contains LiOH, LiaNibCocAdBeO2 which is a positive electrode active material (a, b, c, d, and e satisfy 1.0?a?1.1, 0.45?b?0.90, 0.05?c+d?0.55, and 0?e?0.006, “A” contains at least one of Mn and Al, and “B” contains at least one of Al, Mg, Mo, Ti, W and Zr), and an oxide. The oxide contains at least one of aluminum oxide, magnesium oxide, molybdenum oxide, titanium oxide, tungsten oxide, and zirconium oxide.
    Type: Application
    Filed: December 2, 2016
    Publication date: December 13, 2018
    Applicant: HITACHI AUTOMOTIVE SYSTEMS, LTD.
    Inventors: Naoki KIMURA, Eiji SEKI
  • Publication number: 20180330764
    Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.
    Type: Application
    Filed: July 25, 2018
    Publication date: November 15, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Masato SUGITA, Naoki Kimura, Daisuke Kimura
  • Publication number: 20180323439
    Abstract: Provided are a lithium ion secondary battery that prevents short circuit of a battery in which energy density, cycle characteristics, and safety are all balanced at high levels; and a method for producing the lithium ion secondary battery. The lithium ion secondary battery according to the present invention has a positive electrode, a negative electrode, and a separator provided between the positive electrode and the negative electrode, in which the negative electrode contains a negative electrode active material containing silicon, the hardness of the negative electrode active material is 10 GPa or more and 20 GPa or less, and the separator has a constitution in which a resin layer and a porous layer are laminated, the thickness of the porous layer is 2 ?m or more and 10 ?m or less when the thickness of the resin layer is 25 ?m or more and 30 ?m or less, and the thickness of the porous layer is 5 ?m or more and 20 ?m or less when the thickness of the resin layer is 15 ?m or more but less than 25 ?m.
    Type: Application
    Filed: October 26, 2016
    Publication date: November 8, 2018
    Applicant: Hitachi, Ltd.
    Inventors: Naoki KIMURA, Eiji SEKI
  • Patent number: 10056119
    Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: August 21, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masato Sugita, Naoki Kimura, Daisuke Kimura
  • Publication number: 20180166738
    Abstract: Capacity of a lithium ion secondary battery is increased and life of the lithium ion secondary battery is prolonged. A lithium ion secondary battery includes a negative electrode, a positive electrode, and a separator. The negative electrode contains a silicon-containing Si-based negative electrode active material, graphite, and a negative electrode binder.
    Type: Application
    Filed: August 26, 2016
    Publication date: June 14, 2018
    Inventors: Naoki KIMURA, Eiji SEKI, Seogchul SHIN
  • Patent number: 9971725
    Abstract: A semiconductor device includes a substrate having a serial advanced technology attachment (SATA) connector that has a plurality of power supply terminals and a plurality of signal terminals, a nonvolatile semiconductor memory unit disposed on the substrate, and a memory control circuit disposed on the substrate, configured to control the nonvolatile semiconductor memory unit, and having a data input terminal connected to a first power supply terminal of the SATA connector and a data output terminal connected to a second power supply terminal of the SATA connector. A serial signal of input data is transmitted from the first power supply terminal to the data input terminal, and a serial signal of output data is transmitted from the data output terminal to the second power supply terminal.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: May 15, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Naoki Kimura
  • Publication number: 20180090182
    Abstract: A semiconductor device includes a substrate, a nonvolatile semiconductor memory disposed on a surface of the substrate, and a controller disposed on a surface of the controller. The substrate has a slit on an edge on which interface connection terminals are formed, a ground pattern, first and second wiring patterns that are electrically connected to the ground pattern and extend in a direction in which the slit extends, and a through hole that is formed between the first and second wiring patterns and is large enough along a dimension between the first and second wiring patterns to span substantially all of the spacing between the first and second wiring patterns.
    Type: Application
    Filed: March 2, 2017
    Publication date: March 29, 2018
    Inventor: Naoki KIMURA
  • Publication number: 20180076186
    Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
    Type: Application
    Filed: November 24, 2017
    Publication date: March 15, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Hayato MASUBUCHI, Naoki Kimura, Manabu Matsumoto, Toyota Morimoto
  • Patent number: 9869808
    Abstract: A planar light-emitting unit includes a light emission region and a non-light emission region located in an outer periphery of the light emission region. A non-space region is provided between a light guide member and a diffusion member in a region corresponding to the non-light emission region such that a space is formed in a region corresponding to the light emission region between the light guide member and the diffusion member. The non-space region includes a protruding region extending to the light emission region from the non-light emission region, and a conditional expression 0<??2d×tan ? is fulfilled, where ? is a protruding amount (mm) from the non-light emission region of the non-space region, d is a thickness (mm) of the light guide member, and ? is a total reflection critical angle between the light guide member and air.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: January 16, 2018
    Assignee: KONICA MINOLTA, INC.
    Inventors: Naoki Kimura, Yusuke Hirao, Koujirou Sekine
  • Publication number: 20180004267
    Abstract: According to one embodiment, a memory system includes a volatile memory, a power supply circuit, and a controller. The power supply circuit includes a first power supply path in which power supplied from a host device is supplied to the volatile memory, a second power supply path in which the power is supplied from the internal power supply to the volatile memory, and a switching device that switches between the first power supply path and the second power supply path. In response to an instruction for a transition to a low power consumption mode received from the host device, the controller outputs, to the switching device, an instruction to switch the power supply circuit from the first power supply path to the second power supply path.
    Type: Application
    Filed: September 15, 2017
    Publication date: January 4, 2018
    Applicant: Toshiba Memory Corporation
    Inventor: Naoki KIMURA
  • Patent number: 9859679
    Abstract: A semiconductor laser module 1 has a semiconductor laser device 30 operable to emit a laser beam L having an optical axis along the Z-direction, a collimator lens 40 configured to collimate components of the laser beam L along a direction of a fast axis (Y-direction), and a lens fixture block 50 fixed relative to the semiconductor laser device 30. The lens fixture block 50 has a lens attachment surface 50A perpendicular to the X-direction. An end 40A of the collimator lens 40 along the X-direction is fixed to the lens attachment surface 50A of the lens fixture block 50 with a lens fixation resin 42.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: January 2, 2018
    Assignee: FUJIKURA LTD.
    Inventor: Naoki Kimura
  • Patent number: 9859264
    Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: January 2, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hayato Masubuchi, Naoki Kimura, Manabu Matsumoto, Toyota Morimoto
  • Publication number: 20170309313
    Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.
    Type: Application
    Filed: July 11, 2017
    Publication date: October 26, 2017
    Applicant: Toshiba Memory Corporation
    Inventors: Masato SUGITA, Naoki KIMURA, Daisuke KIMURA
  • Publication number: 20170264060
    Abstract: An interface includes a connector that is physically and electrically connectable to a device conforming to a first interface standard and a device conforming to a second interface standard, and an interface circuit including a signal line extending to a terminal of the connector, a coupling capacitor disposed on the signal line, and a switch having a first end electrically connected to a first terminal of the coupling capacitor and a second end electrically connected to a second terminal of the coupling capacitor. The switch is turned on when the connector is connected to a device conforming to the first interface standard so that a signal bypasses the coupling capacitor and is transmitted through the switch and turned off when the connector is connected to a device conforming to the second interface standard so that the signal is transmitted through the coupling capacitor.
    Type: Application
    Filed: February 1, 2017
    Publication date: September 14, 2017
    Inventor: Naoki KIMURA
  • Patent number: 9754632
    Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: September 5, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hayato Masubuchi, Naoki Kimura, Manabu Matsumoto, Toyota Morimoto
  • Patent number: 9721621
    Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: August 1, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masato Sugita, Naoki Kimura, Daisuke Kimura
  • Publication number: 20170198882
    Abstract: There is obtained a light emitting device including a configuration such that when a viewing angle is changed, a larger colour variation can be presented. The light emitting device comprises: an organic EL panel having a light emitting surface; a light diffusion layer provided on the light emitting surface; and a color difference creation layer provided on the light diffusion layer to receive lights from the light diffusion layer, change the lights in color and thus discharge them to allow a different color to be observed depending on a viewing angle.
    Type: Application
    Filed: June 29, 2015
    Publication date: July 13, 2017
    Inventors: Junya WAKAHARA, Naoki KIMURA
  • Patent number: 9647421
    Abstract: The semiconductor laser module 1 has a first substrate 10, a second substrate 20 provided on the first substrate 10, a semiconductor laser device 30 operable to emit a laser beam L having an optical axis along the Z-direction, a collimator lens 40 configured to collimate components of the laser beam L along a direction of a fast axis (Y-direction), and a lens fixture block 50 having a lens attachment surface 50A and a block fixation surface 50B that are perpendicular to the X-direction. An end 40A of the collimator lens 40 along the X-direction is fixed to the lens attachment surface 50A of the lens fixture block 50 with a lens fixation resin 42. The block fixation surface 50B of the lens fixture block 50 is fixed to a side surface 20A of the second substrate 20 along the X-direction with a block fixation resin 52.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: May 9, 2017
    Assignee: FUJIKURA LTD.
    Inventors: Naoki Kimura, Susumu Nakaya
  • Publication number: 20170123137
    Abstract: A planar light-emitting unit includes a light emission region and a non-light emission region located in an outer periphery of the light emission region. A non-space region is provided between a light guide member and a diffusion member in a region corresponding to the non-light emission region such that a space is formed in a region corresponding to the light emission region between the light guide member and the diffusion member. The non-space region includes a protruding region extending to the light emission region from the non-light emission region, and a conditional expression 0<??2d×tan? is fulfilled, where ? is a protruding amount (mm) from the non-light emission region of the non-space region, d is a thickness (mm) of the light guide member, and ? is a total reflection critical angle between the light guide member and air.
    Type: Application
    Filed: March 17, 2015
    Publication date: May 4, 2017
    Inventors: Naoki KIMURA, Yusuke HIRAO, Koujirou SEKINE
  • Patent number: 9614221
    Abstract: A lithium-ion secondary battery of the present invention contains: a laminated electrode group formed of a rectangular positive electrode; a rectangular negative electrode; and a separator. In such a laminated electrode group, the positive electrode includes a positive electrode current collector foil, and a positive electrode mixture layer containing a positive electrode active material, the negative electrode includes a negative electrode current collector foil, and a negative electrode mixture layer containing a negative electrode active material. The negative electrode active material includes a silicon-based material, and a carbonaceous material. A mass ratio of the silicon-based material and the carbonaceous material is 20:80 to 80:20. The silicon-based material is a Si alloy or SiOx (0.5?x?1.5). The positive electrode and the negative electrode have a collection terminal protruding from a same side of the laminated electrode group.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: April 4, 2017
    Assignee: HITACHI, LTD.
    Inventors: Naoki Kimura, Eiji Seki