Abstract: In this invention, a control unit in an ophthalmic image processing device acquires an ophthalmic image captured by an ophthalmic image capture device (S11). The control unit, by inputting the ophthalmic image into a mathematical model that has been trained by a machine-learning algorithm, acquires a probability distribution in which the random variables are the coordinates at which a specific site and/or a specific boundary of a tissue is present within a region of the ophthalmic image (S14). On the basis of the acquired probability distribution, the control unit detects the specific boundary and/or the specific site (S16, S24).

Abstract: A superjunction semiconductor device having a termination structure portion surrounding an active region in a plan view. The device includes: a semiconductor substrate; a first semiconductor layer provided on the semiconductor substrate; and a parallel pn structure and a channel stopper provided in the first semiconductor layer. The channel stopper surrounds the parallel pn structure in the plan view, and contacts the parallel pn structure in the termination structure portion. The parallel pn structure includes a plurality of first columns each having a first width and a plurality of second columns each having a second width that repeatedly alternate one another parallel to the main surface. In a region of the parallel pn structure contacting the channel stopper, a product of the second width and an impurity concentration of the second columns is less than a product of the first width and an impurity concentration of the first columns.

Abstract: Provided is a gate voltage determination apparatus of a MOS transistor having a gate electrode, a gate insulating film and a channel region, the gate voltage determination apparatus including: a characteristic acquisition unit configured to acquire current-voltage characteristics showing a relationship between a gate current flowing through the gate electrodes and a gate voltage when the gate voltage applied to the gate electrode is changed from a higher voltage side to a lower voltage side; and a voltage determination unit configured to determine, based on a value of the gate voltage at which the gate current shows a peak waveform in the current-voltage characteristics, an off-gate voltage to be applied to the gate electrode when turning off the MOS transistor.

Abstract: A silicon carbide semiconductor device, including a semiconductor substrate, and a first semiconductor region, a plurality of second semiconductor regions, a plurality of third semiconductor regions and a plurality of fourth semiconductor regions formed in the semiconductor substrate. The semiconductor device further includes a plurality of trenches penetrating the second, third and fourth semiconductor regions, a plurality of gate electrodes respectively provided via a plurality of gate insulating films in the trenches, a plurality of fifth semiconductor regions each provided between one of the gate insulating films at the inner wall of one of the trenches, and the third semiconductor region and the fourth semiconductor region through which the one trench penetrates. The semiconductor device further includes first electrodes electrically connected to the second, third and fourth semiconductor regions, and a second electrode provided on a second main surface of the semiconductor substrate.

Abstract: A silicon carbide semiconductor device, including a semiconductor substrate, and a first semiconductor region, a plurality of second semiconductor regions, a plurality of third semiconductor regions and a plurality of fourth semiconductor regions formed in the semiconductor substrate. The semiconductor device further includes a plurality of trenches penetrating the second, third and fourth semiconductor regions, a plurality of gate electrodes respectively provided via a plurality of gate insulating films in the trenches, a plurality of fifth semiconductor regions each provided between one of the gate insulating films at the inner wall of one of the trenches, and the third semiconductor region and the fourth semiconductor region through which the one trench penetrates. The semiconductor device further includes first electrodes electrically connected to the second, third and fourth semiconductor regions, and a second electrode provided on a second main surface of the semiconductor substrate.

Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In the n?-type drift layer, an n-type region, a first p+-type region, and a second p+-type region are provided. A metal film of a trench SBD is connected to a source electrode; and a p+-type region is provided between the source electrode and the p-type base layer.

Abstract: A first side wall and a second side wall of a trench are each an a-plane having high carrier mobility. Along the first side wall of the trench, a gate insulating film is provided. A gate electrode is provided in the trench, and across the gate insulating film, opposes a portion of a p-type base region between an n+-type source region and an n-type current spreading region. Along the second side wall of the trench, a conductive layer is provided. The conductive layer, at the second side wall of the trench, forms Schottky contacts with a p++-type contact region, the p-type base region, and the n-type current spreading region. The trench has a bottom corner portion that is at the second side wall and encompassed by a p+-type region that is provided in the n-type current spreading region so as to be separated from the p-type base region.

Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In the n?-type drift layer, an n-type region, a first p+-type region, and a second p+-type region are provided. A metal film of a trench SBD is connected to a source electrode; and a p+-type region is provided between the source electrode and the p-type base layer.

Abstract: A first side wall and a second side wall of a trench are each an a-plane having high carrier mobility. Along the first side wall of the trench, a gate insulating film is provided. A gate electrode is provided in the trench, and across the gate insulating film, opposes a portion of a p-type base region between an n+-type source region and an n-type current spreading region. Along the second side wall of the trench, a conductive layer is provided. The conductive layer, at the second side wall of the trench, forms Schottky contacts with a p++-type contact region, the p-type base region, and the n-type current spreading region. The trench has a bottom corner portion that is at the second side wall and encompassed by a p+-type region that is provided in the n-type current spreading region so as to be separated from the p-type base region.

Abstract: A semiconductor substrate made of silicon carbide is provided with first and second cells having a MOS gate structure. The first cell is a normal MOSFET cell. In the second cell, a gate electrode is directly connected to a source electrode and has a potential fixed to a potential of the source electrode. A thickness of a gate insulating film of the second cell is set to be less than a thickness of a gate insulating film of a first cell so that the surface potential of a p-type channel region of the second cell becomes lower than the surface potential of a p-type channel region of the first cell during a negative bias to the gate electrode of the first cell.

Abstract: A pulse current application circuit for applying a pulse current to a current application target. The pulse current application circuit includes a first switching element and an inductive load connected in series between a power supply and a reference potential, a second switching element connected in series with the current application target, the second switching element and the current application target being connected between the reference potential and a connection point of the first switching element and the inductive load, and a commutation circuit connected in parallel to the inductive load, the commutation circuit having a current flowing therethrough and having no current flowing therethrough respectively when the second switching element is in a cut-off state and a conductive state.

Abstract: A semiconductor substrate made of silicon carbide is provided with first and second cells having a MOS gate structure. The first cell is a normal MOSFET cell. In the second cell, a gate electrode is directly connected to a source electrode and has a potential fixed to a potential of the source electrode. A thickness of a gate insulating film of the second cell is set to be less than a thickness of a gate insulating film of a first cell so that the surface potential of a p-type channel region of the second cell becomes lower than the surface potential of a p-type channel region of the first cell during a negative bias to the gate electrode of the first cell.

Abstract: A silicon carbide semiconductor device, including a silicon carbide semiconductor structure, an insulated gate structure, an interlayer insulating film formed on the insulated gate structure, a poly-silicon film formed on the interlayer insulating film, and a main electrode formed on the poly-silicon film and in electrical connection with the silicon carbide semiconductor structure. The insulated gate structure includes a gate insulating film, which is a silicon dioxide film contacting the silicon carbide semiconductor structure, and a gate electrode formed on the gate insulating film.

Abstract: A pulse current application circuit for applying a pulse current to a current application target. The pulse current application circuit includes a first switching element and an inductive load connected in series between a power supply and a reference potential, a second switching element connected in series with the current application target, the second switching element and the current application target being connected between the reference potential and a connection point of the first switching element and the inductive load, and a commutation circuit connected in parallel to the inductive load, the commutation circuit having a current flowing therethrough and having no current flowing therethrough respectively when the second switching element is in a cut-off state and a conductive state.

Abstract: A silicon carbide semiconductor device, including a silicon carbide semiconductor structure, an insulated gate structure including a gate insulating film contacting the silicon carbide semiconductor structure and a gate electrode formed on the gate insulating film, an interlayer insulating film covering the insulated gate structure, a metal layer provided on the interlayer insulating film for absorbing or blocking hydrogen, and a main electrode provided on the metal layer and electrically connected to the silicon carbide semiconductor structure.

Abstract: A semiconductor device includes a first drain region that is made primarily of SiC, a drift layer, a channel region, a first source region, a source electrode that is formed on the first source region, a second drain region that is connected to the first source region, a second source region that is formed separated from the second drain region, a first floating electrode that is connected to the second source region and to the channel region, first gate electrodes, and a second gate electrode that is connected to the first gate electrodes.

Abstract: A semiconductor device includes a first drain region that is made primarily of SiC, a drift layer, a channel region, a first source region, a source electrode that is formed on the first source region, a second drain region that is connected to the first source region, a second source region that is formed separated from the second drain region, a first floating electrode that is connected to the second source region and to the channel region, first gate electrodes, and a second gate electrode that is connected to the first gate electrodes.

Abstract: A semiconductor device comprises an n+ type SiC semiconductor substrate, an n type low concentration drift layer of an SiC semiconductor on the substrate, p type channel regions selectively arranged in the drift layer with a specified distance between the channel regions, an n type source region selectively arranged in the channel region, a source electrode in common contact with the source region and the channel region, and a gate electrode disposed over the drift layer between two channel regions, and over a part of the channel region positioned between the drift layer and the source region intercalating a gate oxide film therebetween. The drift layer has a low concentration of at most 70% of the concentration that is required to exhibit a specified withstand voltage at a minimum ON resistance.

Abstract: A silicon carbide semiconductor device, including a silicon carbide semiconductor structure, an insulated gate structure, an interlayer insulating film formed on the insulated gate structure, a poly-silicon film formed on the interlayer insulating film, and a main electrode formed on the poly-silicon film and in electrical connection with the silicon carbide semiconductor structure. The insulated gate structure includes a gate insulating film, which is a silicon dioxide film contacting the silicon carbide semiconductor structure, and a gate electrode formed on the gate insulating film.

Abstract: A silicon carbide semiconductor device, including a silicon carbide semiconductor structure, an insulated gate structure including a gate insulating film contacting the silicon carbide semiconductor structure and a gate electrode formed on the gate insulating film, an interlayer insulating film covering the insulated gate structure, a metal layer provided on the interlayer insulating film for absorbing or blocking hydrogen, and a main electrode provided on the metal layer and electrically connected to the silicon carbide semiconductor structure.