Patents by Inventor Naoki Kumagai

Naoki Kumagai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200359999
    Abstract: A physiological information system includes a patient monitor configured to acquire a vital sign based on a vital sign signal of a subject, and an ultrasonic measuring apparatus configured to acquire ultrasonic images based on ultrasonic waves transmitted toward the subject and received from the subject. The patient monitor includes a storage device configured to store measured data of the vital signs in association with measurement dates and times, and to store the ultrasonic images in association with image capture timings, and a controller configured to display a screen on a display section based on data, including the measured data and the ultrasonic images, stored in the storage device.
    Type: Application
    Filed: November 13, 2018
    Publication date: November 19, 2020
    Inventors: Mitsuhiro OURA, Sou KUMAGAI, Wataru MATSUZAWA, Nobuyuki YASUMARU, Kazuya NAGASE, Hiroshi TORIGAI, Naoki FUKUSHIMA
  • Patent number: 10770582
    Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In the n?-type drift layer, an n-type region, a first p+-type region, and a second p+-type region are provided. A metal film of a trench SBD is connected to a source electrode; and a p+-type region is provided between the source electrode and the p-type base layer.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: September 8, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke Kobayashi, Manabu Takei, Naoki Kumagai
  • Patent number: 10770581
    Abstract: A first side wall and a second side wall of a trench are each an a-plane having high carrier mobility. Along the first side wall of the trench, a gate insulating film is provided. A gate electrode is provided in the trench, and across the gate insulating film, opposes a portion of a p-type base region between an n+-type source region and an n-type current spreading region. Along the second side wall of the trench, a conductive layer is provided. The conductive layer, at the second side wall of the trench, forms Schottky contacts with a p++-type contact region, the p-type base region, and the n-type current spreading region. The trench has a bottom corner portion that is at the second side wall and encompassed by a p+-type region that is provided in the n-type current spreading region so as to be separated from the p-type base region.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: September 8, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke Kobayashi, Manabu Takei, Shinsuke Harada, Naoki Kumagai
  • Publication number: 20200275908
    Abstract: An ultrasonic measurement system includes a display device configured to display an ultrasonic image and an ultrasonic probe electrically connectable to the display device. The ultrasonic probe includes an image capturing unit joined to or detachably attached to a first cable, the image capturing unit comprising a first optical lens to capture an image of a nearby object, and a probe head joined to or detachably attached to the first cable, the probe head being configured to transmit an ultrasonic beam toward a body surface of a subject and to receive a reflected wave from the body surface.
    Type: Application
    Filed: November 9, 2018
    Publication date: September 3, 2020
    Inventors: Mitsuhiro OURA, Sou KUMAGAI, Wataru MATSUZAWA, Nobuyuki YASUMARU, Kazuya NAGASE, Hiroshi TORIGAI, Naoki FUKUSHIMA, Masashi SATO, Takuya AIZAWA
  • Publication number: 20200245858
    Abstract: A processor of an ophthalmologic image processing device acquires an ophthalmologic image photographed by an ophthalmologic image photographing device. The processor inputs the ophthalmologic image into a mathematical model trained by a machine learning algorithm to acquire a result of an analysis relating to at least one of a specific disease and a specific structure of a subject eye. The processor acquires information of a distribution of weight relating to an analysis by a mathematical model, as supplemental distribution information, for which an image area of the ophthalmologic image input into the mathematical model is set as a variable. The processor sets a part of the image area of the ophthalmologic image, as an attention area, based on the supplemental distribution information. The processor acquires an image of a tissue including the attention area among a tissue of the subject eye and displays the image on a display unit.
    Type: Application
    Filed: January 31, 2020
    Publication date: August 6, 2020
    Applicant: NIDEK CO., LTD.
    Inventors: Naoki Takeno, Ryosuke Shiba, Sohei Miyazaki, Yusuke Sakashita, Yoshiki Kumagai
  • Patent number: 10648388
    Abstract: An object of the present invention is to provide an exhaust system component having excellent properties to be located in an exhaust flow path from an internal combustion engine, particularly, an exhaust system component having an extended use-life. The exhaust system component of the present invention for an internal combustion engine has a self-healing ceramic material and an electric heater for heating the self-healing ceramic material. In particular, the exhaust system component of the present invention is an oxygen sensor having a detection element and an electric heater, wherein the detection element has a solid electrolyte layer, a reference-side electrode layer, an exhaust-side electrode layer, and a diffusion layer and/or a trap layer each composed of a self-healing ceramic material.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: May 12, 2020
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Naoki Takeuchi, Noriaki Kumagai, Go Hayashita, Masakazu Tabata, Hirokazu Ito, Kazuhiro Sugimoto, Hiroki Murata
  • Publication number: 20200083369
    Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In the n?-type drift layer, an n-type region, a first p+-type region, and a second p+-type region are provided. A metal film of a trench SBD is connected to a source electrode; and a p+-type region is provided between the source electrode and the p-type base layer.
    Type: Application
    Filed: July 22, 2019
    Publication date: March 12, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke Kobayashi, Manabu Takei, Naoki Kumagai
  • Publication number: 20200083368
    Abstract: A first side wall and a second side wall of a trench are each an a-plane having high carrier mobility. Along the first side wall of the trench, a gate insulating film is provided. A gate electrode is provided in the trench, and across the gate insulating film, opposes a portion of a p-type base region between an n+-type source region and an n-type current spreading region. Along the second side wall of the trench, a conductive layer is provided. The conductive layer, at the second side wall of the trench, forms Schottky contacts with a p++-type contact region, the p-type base region, and the n-type current spreading region. The trench has a bottom corner portion that is at the second side wall and encompassed by a p+-type region that is provided in the n-type current spreading region so as to be separated from the p-type base region.
    Type: Application
    Filed: July 22, 2019
    Publication date: March 12, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke KOBAYASHI, Manabu TAKEI, Shinsuke HARADA, Naoki KUMAGAI
  • Publication number: 20200037872
    Abstract: An OCT apparatus includes an OCT optical system that has a light splitter splitting light from an OCT light source to light travelling to a measurement light path and light travelling to a reference light path and a detector detecting a spectrum interference signal of measurement light guided to a subject eye through the measurement light path and reference light from the reference light path, and a processing unit that processes the spectrum interference signal to generate OCT data. The processing unit performs at least complementary processing on an overlapping region of a real image and a virtual image in OCT data based on a plurality of OCT data obtained with different optical path lengths when detecting the spectrum interference signal, and generates OCT data subjected to the complementary processing.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 6, 2020
    Applicant: NIDEK CO., LTD.
    Inventors: Ryosuke SHIBA, Masaaki HANEBUCHI, Naoki TAKENO, Yoshiki KUMAGAI
  • Patent number: 10522672
    Abstract: A semiconductor substrate made of silicon carbide is provided with first and second cells having a MOS gate structure. The first cell is a normal MOSFET cell. In the second cell, a gate electrode is directly connected to a source electrode and has a potential fixed to a potential of the source electrode. A thickness of a gate insulating film of the second cell is set to be less than a thickness of a gate insulating film of a first cell so that the surface potential of a p-type channel region of the second cell becomes lower than the surface potential of a p-type channel region of the first cell during a negative bias to the gate electrode of the first cell.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: December 31, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Naoki Kumagai
  • Patent number: 10461645
    Abstract: A power supply system for recovering degraded performance of a solar cell due to PID is provided. The power supply system includes a solar cell, a non-isolated type DC/DC converter that boosts a DC voltage from the solar cell input from an input end with a predetermined boosting ratio and outputs a DC voltage from an output end, and an inverter that converts a DC voltage output from the output end of the DC/DC converter into an AC voltage, the power supply system being connected to an external power system for system interconnection, wherein the power supply system includes a potential adjustment device for applying a voltage of an external power system to the solar cell via the inverter to set a ground potential of a negative electrode of the solar cell to positive when an output of the solar cell is smaller than a predetermined value.
    Type: Grant
    Filed: November 23, 2017
    Date of Patent: October 29, 2019
    Assignee: OMRON Corporation
    Inventors: Yasuhiro Tsubota, Kenji Kobayashi, Takuji Kumagai, Naoki Maki, Kazumi Tsuchimichi
  • Patent number: 10451665
    Abstract: A pulse current application circuit for applying a pulse current to a current application target. The pulse current application circuit includes a first switching element and an inductive load connected in series between a power supply and a reference potential, a second switching element connected in series with the current application target, the second switching element and the current application target being connected between the reference potential and a connection point of the first switching element and the inductive load, and a commutation circuit connected in parallel to the inductive load, the commutation circuit having a current flowing therethrough and having no current flowing therethrough respectively when the second switching element is in a cut-off state and a conductive state.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: October 22, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Naoki Kumagai
  • Publication number: 20190156935
    Abstract: A patient monitor is connectable to an imaging unit. The patient monitor includes a folder creating section and a file operating section. When a first event occurs, the folder creating section newly creates a first folder in a first hierarchy of a file system. When a second event occurs, the folder creating section newly creates a second folder in the first folder that is last created. The file operating section stores an image file relating to image information that is supplied from the imaging unit, in the second folder last created by the folder creating section.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 23, 2019
    Inventors: Mitsuhiro OURA, Sou KUMAGAI, Wataru MATUZAWA, Nobuyuki YASUMARU, Kazuya NAGASE, Hiroshi TORIGAI, Naoki FUKUSHIMA
  • Publication number: 20190081170
    Abstract: A semiconductor substrate made of silicon carbide is provided with first and second cells having a MOS gate structure. The first cell is a normal MOSFET cell. In the second cell, a gate electrode is directly connected to a source electrode and has a potential fixed to a potential of the source electrode. A thickness of a gate insulating film of the second cell is set to be less than a thickness of a gate insulating film of a first cell so that the surface potential of a p-type channel region of the second cell becomes lower than the surface potential of a p-type channel region of the first cell during a negative bias to the gate electrode of the first cell.
    Type: Application
    Filed: August 7, 2018
    Publication date: March 14, 2019
    Applicant: Fuji Electric Co., Ltd.
    Inventor: Naoki KUMAGAI
  • Patent number: 10147797
    Abstract: A silicon carbide semiconductor device, including a silicon carbide semiconductor structure, an insulated gate structure, an interlayer insulating film formed on the insulated gate structure, a poly-silicon film formed on the interlayer insulating film, and a main electrode formed on the poly-silicon film and in electrical connection with the silicon carbide semiconductor structure. The insulated gate structure includes a gate insulating film, which is a silicon dioxide film contacting the silicon carbide semiconductor structure, and a gate electrode formed on the gate insulating film.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: December 4, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takumi Fujimoto, Naoki Kumagai
  • Publication number: 20180340972
    Abstract: A pulse current application circuit for applying a pulse current to a current application target. The pulse current application circuit includes a first switching element and an inductive load connected in series between a power supply and a reference potential, a second switching element connected in series with the current application target, the second switching element and the current application target being connected between the reference potential and a connection point of the first switching element and the inductive load, and a commutation circuit connected in parallel to the inductive load, the commutation circuit having a current flowing therethrough and having no current flowing therethrough respectively when the second switching element is in a cut-off state and a conductive state.
    Type: Application
    Filed: May 1, 2018
    Publication date: November 29, 2018
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Naoki KUMAGAI
  • Patent number: 10096680
    Abstract: A silicon carbide semiconductor device, including a silicon carbide semiconductor structure, an insulated gate structure including a gate insulating film contacting the silicon carbide semiconductor structure and a gate electrode formed on the gate insulating film, an interlayer insulating film covering the insulated gate structure, a metal layer provided on the interlayer insulating film for absorbing or blocking hydrogen, and a main electrode provided on the metal layer and electrically connected to the silicon carbide semiconductor structure.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: October 9, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Naoki Kumagai, Takashi Tsutsumi, Yoshiyuki Sakai, Yasuhiko Oonishi, Takumi Fujimoto, Kenji Fukuda, Shinsuke Harada, Mitsuo Okamoto
  • Patent number: 9825025
    Abstract: A semiconductor device includes a first drain region that is made primarily of SiC, a drift layer, a channel region, a first source region, a source electrode that is formed on the first source region, a second drain region that is connected to the first source region, a second source region that is formed separated from the second drain region, a first floating electrode that is connected to the second source region and to the channel region, first gate electrodes, and a second gate electrode that is connected to the first gate electrodes.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: November 21, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Naoki Kumagai
  • Publication number: 20170271324
    Abstract: A semiconductor device includes a first drain region that is made primarily of SiC, a drift layer, a channel region, a first source region, a source electrode that is formed on the first source region, a second drain region that is connected to the first source region, a second source region that is formed separated from the second drain region, a first floating electrode that is connected to the second source region and to the channel region, first gate electrodes, and a second gate electrode that is connected to the first gate electrodes.
    Type: Application
    Filed: February 9, 2017
    Publication date: September 21, 2017
    Applicant: Fuji Electric Co., Ltd.
    Inventor: Naoki KUMAGAI
  • Patent number: 9761705
    Abstract: A semiconductor device comprises an n+ type SiC semiconductor substrate, an n type low concentration drift layer of an SiC semiconductor on the substrate, p type channel regions selectively arranged in the drift layer with a specified distance between the channel regions, an n type source region selectively arranged in the channel region, a source electrode in common contact with the source region and the channel region, and a gate electrode disposed over the drift layer between two channel regions, and over a part of the channel region positioned between the drift layer and the source region intercalating a gate oxide film therebetween. The drift layer has a low concentration of at most 70% of the concentration that is required to exhibit a specified withstand voltage at a minimum ON resistance.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: September 12, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Naoki Kumagai