Abstract: An n? drift region is disposed on the front surface of an n+ semiconductor substrate composed of a wide band gap semiconductor. A p-channel region is selectively disposed on the surface layer of the n? drift region. A high-concentration p+ base region is disposed so as to adjoin the lower portion of the p-channel region inside the n? drift region. Inside the high-concentration p+ base region, an n+ high-concentration region is selectively disposed at the n+ semiconductor substrate side. The n+ high-concentration region has a stripe-shaped planar layout extending to the direction that the high-concentration p+ base regions line up. The n+ high-concentration region adjoins a JFET region at one end portion in longitudinal direction of the stripe. Further, the n+ semiconductor substrate side of the n+ high-concentration region adjoins the part sandwiched between the high-concentration p+ base region and the n+ semiconductor substrate in the n? drift region.

Abstract: A semiconductor device comprises an n+ type SiC semiconductor substrate, an n type low concentration drift layer of an SiC semiconductor on the substrate, p type channel regions selectively arranged in the drift layer with a specified distance between the channel regions, an n type source region selectively arranged in the channel region, a source electrode in common contact with the source region and the channel region, and a gate electrode disposed over the drift layer between two channel regions, and over a part of the channel region positioned between the drift layer and the source region intercalating a gate oxide film therebetween. The drift layer has a low concentration of at most 70% of the concentration that is required to exhibit a specified withstand voltage at a minimum ON resistance.

Abstract: In aspects of the invention, a zap circuit and a decoder for decoding the output of the zap circuit turn ON only one analog switch in a selector. The selector delivers an electric potential at a node of a dividing resistor selected by the zap circuit. The output of the selector is delivered to the non-inverting input of an operational amplifier, and the output of the operational amplifier is delivered to the gate terminal of a MOSFET. The operational amplifier controls the gate of the MOSFET so that the potential at a current detecting resistor equals the output of the selector. As a result, a current proportional to the input voltage flows through the MOSFET. Because the current through a dividing resistor is also proportional to the input voltage, the total current is eventually proportional to the input voltage.

Abstract: A semiconductor device comprises an n+ type SiC semiconductor substrate, an n type low concentration drift layer of an SiC semiconductor on the substrate, p type channel regions selectively arranged in the drift layer with a specified distance between the channel regions, an n type source region selectively arranged in the channel region, a source electrode in common contact with the source region and the channel region, and a gate electrode disposed over the drift layer between two channel regions, and over a part of the channel region positioned between the drift layer and the source region intercalating a gate oxide film therebetween. The drift layer has a low concentration of at most 70% of the concentration that is required to exhibit a specified withstand voltage at a minimum ON resistance.

Abstract: A wide bandgap insulated gate semiconductor device includes a semiconductor substrate made of semiconductor having a bandgap wider than silicon; n? drift layer over the semiconductor substrate; p-channel regions selectively disposed over the drift layer; n+ semiconductor regions selectively disposed in respective surfaces in the channel regions; a plurality of p+ base regions in contact with bottoms of the respective channel regions; a protruding drift layer portion that is n-type region interposed between the p-channel regions and the p+ base regions thereunder; a gate electrode formed, through a gate insulating film, on the protruding drift layer portion and on respective surfaces of the p-channel regions; a source electrode in contact with the n+ semiconductor regions in the channel regions; and a p+ floating region inside the protruding drift layer portion, having side faces respectively facing side faces of the second conductivity type base regions, wherein respective gaps between the p+ base regions and

Abstract: A wide bandgap insulated gate semiconductor device includes a semiconductor substrate made of semiconductor having a bandgap wider than silicon; n? drift layer over the semiconductor substrate; p-channel regions selectively disposed over the drift layer; n+ semiconductor regions selectively disposed in respective surfaces in the channel regions; a plurality of p+ base regions in contact with bottoms of the respective channel regions; a protruding drift layer portion that is n-type region interposed between the p-channel regions and the p+ base regions thereunder; a gate electrode formed, through a gate insulating film, on the protruding drift layer portion and on respective surfaces of the p-channel regions; a source electrode in contact with the n+ semiconductor regions in the channel regions; and a p+ floating region inside the protruding drift layer portion, having side faces respectively facing side faces of the second conductivity type base regions, wherein respective gaps between the p+ base regions and

Abstract: A wide bandgap insulated gate semiconductor device includes a semiconductor substrate made of semiconductor having a bandgap wider than silicon; n? drift layer over the semiconductor substrate; p-channel regions selectively disposed over the drift layer; n+ semiconductor regions selectively disposed in respective surfaces in the channel regions; a plurality of p+ base regions in contact with bottoms of the respective channel regions; a protruding drift layer portion that is n-type region interposed between the p-channel regions and the p+ base regions thereunder; a gate electrode formed, through a gate insulating film, on the protruding drift layer portion and on respective surfaces of the p-channel regions; a source electrode in contact with the n+ semiconductor regions in the channel regions; and a p+ floating region inside the protruding drift layer portion, having side faces respectively facing side faces of the second conductivity type base regions, wherein respective gaps between the p+ base regions and

Abstract: An n? drift region is disposed on the front surface of an n+ semiconductor substrate composed of a wide band gap semiconductor. A p-channel region is selectively disposed on the surface layer of the n? drift region. A high-concentration p+ base region is disposed so as to adjoin the lower portion of the p-channel region inside the n? drift region. Inside the high-concentration p+ base region, an n+ high-concentration region is selectively disposed at the n+ semiconductor substrate side. The n+ high-concentration region has a stripe-shaped planar layout extending to the direction that the high-concentration p+ base regions line up. The n+ high-concentration region adjoins a JFET region at one end portion in longitudinal direction of the stripe. Further, the n+ semiconductor substrate side of the n+ high-concentration region adjoins the part sandwiched between the high-concentration p+ base region and the n+ semiconductor substrate in the n? drift region.

Abstract: In aspects of the invention, a zap circuit and a decoder for decoding the output of the zap circuit turn ON only one analog switch in a selector. The selector delivers an electric potential at a node of a dividing resistor selected by the zap circuit. The output of the selector is delivered to the non-inverting input of an operational amplifier, and the output of the operational amplifier is delivered to the gate terminal of a MOSFET. The operational amplifier controls the gate of the MOSFET so that the potential at a current detecting resistor equals the output of the selector. As a result, a current proportional to the input voltage flows through the MOSFET. Because the current through a dividing resistor is also proportional to the input voltage, the total current is eventually proportional to the input voltage.

Abstract: A wide bandgap insulated gate semiconductor device includes a semiconductor substrate made of semiconductor having a bandgap wider than silicon; n? drift layer over the semiconductor substrate; p-channel regions selectively disposed over the drift layer; n+ semiconductor regions selectively disposed in respective surfaces in the channel regions; a plurality of p+ base regions in contact with bottoms of the respective channel regions; a protruding drift layer portion that is n-type region interposed between the p-channel regions and the p+ base regions thereunder; a gate electrode formed, through a gate insulating film, on the protruding drift layer portion and on respective surfaces of the p-channel regions; a source electrode in contact with the n+ semiconductor regions in the channel regions; and a p+ floating region inside the protruding drift layer portion, having side faces respectively facing side faces of the second conductivity type base regions, wherein respective gaps between the p+ base regions and

Abstract: A semiconductor device comprises an n+ type SiC semiconductor substrate, an n type low concentration drift layer of an SiC semiconductor on the substrate, p type channel regions selectively arranged in the drift layer with a specified distance between the channel regions, an n type source region selectively arranged in the channel region, a source electrode in common contact with the source region and the channel region, and a gate electrode disposed over the drift layer between two channel regions, and over a part of the channel region positioned between the drift layer and the source region intercalating a gate oxide film therebetween. The drift layer has a low concentration of at most 70% of the concentration that is required to exhibit a specified withstand voltage at a minimum ON resistance.

Abstract: A gate drive device which can suppress the fluctuation of an internal power source voltage and output voltage, while reducing the number of parts by omitting a bypass capacitor connected in parallel with a semiconductor integrated circuit, is provided. The gate drive device drives the gate of an active element with a large input capacity, such as an IGBT or MOSFET, and includes a semiconductor integrated circuit. The semiconductor integrated circuit has an internal power source based on an external power source, such as a battery. The semiconductor integrated circuit incorporates a voltage drop suppressing circuit, configured so that, if an input external power source voltage momentarily drops below a minimum operating voltage, a drop of an internal power source voltage below the minimum operating voltage, and a sharp drop in a voltage output to the gate, are prevented by the voltage drop suppressing circuit.

Abstract: A gate drive device which can suppress the fluctuation of an internal power source voltage and output voltage, while reducing the number of parts by omitting a bypass capacitor connected in parallel with a semiconductor integrated circuit, is provided. The gate drive device drives the gate of an active element with a large input capacity, such as an IGBT or MOSFET, and includes a semiconductor integrated circuit. The semiconductor integrated circuit has an internal power source based on an external power source, such as a battery. The semiconductor integrated circuit incorporates a voltage drop suppressing circuit, configured so that, if an input external power source voltage momentarily drops below a minimum operating voltage, a drop of an internal power source voltage below the minimum operating voltage, and a sharp drop in a voltage output to the gate, are prevented by the voltage drop suppressing circuit.

Abstract: The shape of a tip of an insulating material of an insulating isolation region is provided as being a concave one recessed below the back surface of an n-semiconductor substrate. This reduces the electric field strength at the corner at which the bottom of the n-semiconductor substrate is in contact with the insulating isolation region to allow an excellent breakdown voltage to be obtained. Moreover, by forming a high impurity concentration region such as a field-stop layer on the back surface of the n-semiconductor substrate, a depletion layer extending from the top surface is prevented from reaching the back surface. This eliminates an influence of a surface state introduced in the interface between the insulator film formed on the back surface and the n-semiconductor substrate, by which an excellent breakdown voltage can be obtained.

Abstract: To prevent the destruction of a semiconductor element due to negative resistance, and to reduce the dynamic resistance of a static electricity prevention diode, the ratio of the maximum electric field intensity during an avalanche and the average electric field in a strong electric field region, as well as the impurity density gradient in the vicinity of the strong electric field region are optimized. During avalanche breakdown, a depletion layer is formed across the entire high resistivity region, and its average electric field is kept to ½ or more of the maximum electric field intensity. The density gradients (the depths and impurity densities) of a p+ region and of an n+ region that form a p-n junction of the diode are controlled so that the density gradient in the neighborhood of the high resistivity region does not have negative resistance with respect to increase of the avalanche current.

Abstract: A semiconductor device is configured to prevent destruction of elements and/or miss-operation of the circuit by parasitic effects produced by parasitic transistors when a MOSFET of a bridge circuit is formed on a single chip. A Schottky junction is formed by providing an anode electrode in an n well region where a source region, a drain region, and a p well region of a lateral MOSFET. A Schottky barrier diode constituting a majority carrier device is connected in parallel with a PN junction capable of being forward-biased so that the PN junction is not forward-biased so that minority carriers are not generated, and thereby suppressing parasitic effects.

Abstract: A lateral MOSFET and a method of forming thereof includes a p-type semiconductor substrate, a first n-type well in the surface portion of the semiconductor substrate, an n+-type drain region in the first n-type well, a p-type well in the first n-type well, an n+-type source region in the p-type well, a gate oxide film on the portion of the p-type well between the n+-type source region and the first n-type well, a gate electrode on the gate oxide film, and a second n-type well containing the p-type well therein to increase the n-type impurity concentration in the vicinity of the junction between the p-type well and the first n-type well beneath the gate and to increase the impurity amount and the thickness of the n-type semiconductor region beneath the p-type well. The first and second n-type wells can be overlapping or formed continuous or contiguous with each other. The lateral MOSFET exhibits a high punch-through breakdown voltage suitable for a high-side switch.

Abstract: A semiconductor device realizes a high electrostatic discharge withstanding capability and a high surge withstanding capability within the narrow chip area of a lateral MOSFET used in integrated intelligent switching devices, double-integration-type signal input and transfer IC's, and combined power IC's. The semiconductor device includes a vertical bipolar transistor in which a base is electrically connected to an emitter and a collector, and a lateral MOSFET including a drain electrode connected to a surface electrode. The vertical bipolar transistor absorbs electrostatic discharge or surge energy when a high electrostatic discharge voltage or a high surge voltage is applied and limits the electrostatic discharge voltage or the surge voltage to be lower than the breakdown voltage of the lateral MOSFET.

Abstract: The shape of a tip of an insulating material of an insulating isolation region is provided as being a concave one recessed below the back surface of an n-semiconductor substrate. This reduces the electric field strength at the corner at which the bottom of the n-semiconductor substrate is in contact with the insulating isolation region to allow an excellent breakdown voltage to be obtained. Moreover, by forming a high impurity concentration region such as a field-stop layer on the back surface of the n-semiconductor substrate, a depletion layer extending from the top surface is prevented from reaching the back surface This eliminates an influence of a surface state introduced in the interface between the insulator film formed on the back surface and the n-semiconductor substrate, by which an excellent breakdown voltage can be obtained.

Abstract: To prevent the destruction of a semiconductor element due to negative resistance, and to reduce the dynamic resistance of a static electricity prevention diode, the ratio of the maximum electric field intensity during an avalanche and the average electric field in a strong electric field region, as well as the impurity density gradient in the vicinity of the strong electric field region are optimized. During avalanche breakdown, a depletion layer is formed across the entire high resistivity region, and its average electric field is kept to ½ or more of the maximum electric field intensity. The density gradients (the depths and impurity densities) of a p+ region and of an n+ region that form a p-n junction of the diode are controlled so that the density gradient in the neighborhood of the high resistivity region does not have negative resistance with respect to increase of the avalanche current.