Abstract: A lateral MOSFET and a method of forming thereof includes a p-type semiconductor substrate, a first n-type well in the surface portion of the semiconductor substrate, an n+-type drain region in the first n-type well, a p-type well in the first n-type well, an n+-type source region in the p-type well, a gate oxide film on the portion of the p-type well between the n+-type source region and the first n-type well, a gate electrode on the gate oxide film, and a second n-type well containing the p-type well therein to increase the n-type impurity concentration in the vicinity of the junction between the p-type well and the first n-type well beneath the gate and to increase the impurity amount and the thickness of the n-type semiconductor region beneath the p-type well. The first and second n-type wells can be overlapping or formed continuous or contiguous with each other. The lateral MOSFET exhibits a high punch-through breakdown voltage suitable for a high-side switch.

Abstract: A semiconductor device realizes a high electrostatic discharge withstanding capability and a high surge withstanding capability within the narrow chip area of a lateral MOSFET used in integrated intelligent switching devices, double-integration-type signal input and transfer IC's, and combined power IC's. The semiconductor device includes a vertical bipolar transistor in which a base is electrically connected to an emitter and a collector, and a lateral MOSFET including a drain electrode connected to a surface electrode. The vertical bipolar transistor absorbs electrostatic discharge or surge energy when a high electrostatic discharge voltage or a high surge voltage is applied and limits the electrostatic discharge voltage or the surge voltage to be lower than the breakdown voltage of the lateral MOSFET.

Abstract: A semiconductor device realizes a high electrostatic discharge withstanding capability and a high surge withstanding capability within the narrow chip area of a lateral MOSFET used in integrated intelligent switching devices, double-integration-type signal input and transfer IC's, and combined power IC's. The semiconductor device includes a vertical bipolar transistor in which a base is electrically connected to an emitter and a collector, and a lateral MOSFET including a drain electrode connected to a surface electrode. The vertical bipolar transistor absorbs electrostatic discharge or surge energy when a high electrostatic discharge voltage or a high surge voltage is applied and limits the electrostatic discharge voltage or the surge voltage to be lower than the breakdown voltage of the lateral MOSFET.

Abstract: An intelligent power module includes semiconductor switching devices, drive circuits, a variety of detecting circuits and warning circuits for detecting a fatal abnormal condition and a precursory abnormal condition thereof in the switching devices, the drive circuits and so forth, abnormal condition detecting logic devices and drive circuits for protecting the switching devices when the detecting circuits and the warning circuits detect the abnormal condition, and control circuits and a transmission circuit for outputting a signal based on detection of the abnormal condition. The transmission circuit has an output terminal for outputting alarm signals when the fatal abnormal condition is detected, and an output terminal for outputting abnormality factor discrimination signals indicating abnormality factors contributing to the fatal abnormal condition and the precursory abnormal condition.

Abstract: A semiconductor device is configured to prevent destruction of elements and/or miss-operation of the circuit by parasitic effects produced by parasitic transistors when a MOSFET of a bridge circuit is formed on a single chip. A Schottky junction is formed by providing an anode electrode in an n well region where a source region, a drain region, and a p well region of a lateral MOSFET. A Schottky barrier diode constituting a majority carrier device is connected in parallel with a PN junction capable of being forward-biased so that the PN junction is not forward-biased so that minority carriers are not generated, and thereby suppressing parasitic effects.

Abstract: A semiconductor device is configured to prevent destruction of elements and/or miss-operation of the circuit by parasitic effects produced by parasitic transistors when a MOSFET of a bridge circuit is formed on a single chip. A Schottky junction is formed by providing an anode electrode in an n well region where a source region, a drain region, and a p well region of a lateral MOSFET. A Schottky barrier diode constituting a majority carrier device is connected in parallel with a PN junction capable of being forward-biased so that the PN junction is not forward-biased so that minority carriers are not generated, and thereby suppressing parasitic effects.

Abstract: A semiconductor device realizes a high electrostatic discharge withstanding capability and a high surge withstanding capability within the narrow chip area of a lateral MOSFET used in integrated intelligent switching devices, double-integration-type signal input and transfer IC's, and combined power IC's. The semiconductor device includes a vertical bipolar transistor in which a base is electrically connected to an emitter and a collector, and a lateral MOSFET including a drain electrode connected to a surface electrode. The vertical bipolar transistor absorbs electrostatic discharge or surge energy when a high electrostatic discharge voltage or a high surge voltage is applied and limits the electrostatic discharge voltage or the surge voltage to be lower than the breakdown voltage of the lateral MOSFET.

Abstract: A semiconductor device is configured to prevent destruction of elements and/or miss-operation of the circuit by parasitic effects produced by parasitic transistors when a MOSFET of a bridge circuit is formed on a single chip. A Schottky junction is formed by providing an anode electrode in an n well region where a source region, a drain region, and a p well region of a lateral MOSFET. A Schottky barrier diode constituting a majority carrier device is connected in parallel with a PN junction capable of being forward-biased so that the PN junction is not forward-biased so that minority carriers are not generated, and thereby suppressing parasitic effects.

Abstract: A drive circuit drives a voltage-controlled semiconductor switching device with a control terminal. The drive circuit includes a device for supplying a current to the control terminal based on an input of an ON signal, and a device for removing a current from the control terminal of the voltage-controlled semiconductor switching device based on an input of an OFF signal. The current-supplying device includes a voltage-controlled transistor having a gate electrode and a drain electrode connected to the control terminal, and a capacitor connected between the gate and drain electrodes of the voltage-controlled transistor. It is possible to reduce turn-on losses during the turn-on time of the switching device while reducing noises generated thereat.

Abstract: A level shift circuit applies an on signal 25 and an off signal 26 each consisting of pulses, to high-voltage MOSFETs 1, 2, respectively, having their source connected to a common potential COM to induce a voltage drop in load resistors 3, 4 in order to set or reset a RS latch 15 to turn on or off an IGBT 17 on an upper arm of a PWM inverter bridge circuit having a varying emitter potential, a circuit free from a long time delay prevents an increase dV/dt in potential of an AC output terminal OUT that results in charging of a capacity between a source and a drain of each of the high-voltage MOSFETs 1, 2, whereby the charge current induces a voltage drop in the resistors 3, 4 to cause the RS latch to malfunction. NOT circuits 8, 11 and a NOR circuit 13 transmit a regular on signal, while NOT circuits 9, 12 and a NOR circuit 14 transmit a regular off signal.

Abstract: A dry radioactive substance storage facility stores spent fuel assemblies from nuclear power plants. The facility comprises a structure having a storage room storing storage tubes containing spent fuel assemblies. An air inlet duct defining an air inlet passage through which air is supplied into the storage room and a stack defining an air discharge passage through which air from the storage room is discharged outside are connected to the storage room. Radiation shielding members are disposed on the side of the air inlet duct and on the side of the stack, respectively, in the storage room to intercept radiation propagating toward the air inlet passage and the air discharge passage.

Abstract: A dry radioactive substance storage facility stores spent fuel assemblies from nuclear power plants. The facility comprises a structure having a storage room storing storage tubes containing spent fuel assemblies. An air inlet duct defining an air inlet passage through which air is supplied into the storage room and an stack defining an air discharge passage through which air from the storage room is discharged outside are connected to the storage room. Radiation shielding members are disposed on the side of the air inlet duct and on the side of the stack, respectively, in the storage room to intercept radiation propagating toward the air inlet passage and the air discharge passage.

Abstract: A dry radioactive substance storage facility stores spent fuel assemblies from nuclear power plants. The facility comprises a structure having a storage room storing storage tubes containing spent fuel assemblies. An air inlet duct defining an air inlet passage through which air is supplied into the storage room and an stack defining an air discharged passage through which air from the storage room is discharge outside are connected to the storage room. Radiation shielding members are disposed on the side of the air inlet duct and on the side of the stack, respectively, in the storage room to intercept radiation propagating toward the air inlet passage and the air discharge passage.

Abstract: An intelligent power module includes semiconductor switching devices, drive circuits, a variety of detecting circuits and warning circuits for detecting a fatal abnormal condition and a precursory abnormal condition thereof in the switching devices, the drive circuits and so forth, abnormal condition detecting logic devices and drive circuits for protecting the switching devices when the detecting circuits and the warning circuits detect the abnormal condition, and control circuits and a transmission circuit for outputting a signal based on detection of the abnormal condition. The transmission circuit has an output terminal for outputting alarm signals when the fatal abnormal condition is detected, and an output terminal for outputting abnormality factor discrimination signals indicating abnormality factors contributing to the fatal abnormal condition and the precursory abnormal condition.

Abstract: A level shift circuit applies an on signal 25 and an off signal 26 each consisting of pulses, to high-voltage MOSFETs 1, 2, respectively, having their source connected to a common potential COM to induce a voltage drop in load resistors 3, 4 in order to set or reset a RS latch 15 to turn on or off an IGBT 17 on an upper arm of a PWM inverter bridge circuit having a varying emitter potential, a circuit free from a long time delay prevents an increase dV/dt in potential of an AC output terminal OUT that results in charging of a capacity between a source and a drain of each of the high-voltage MOSFETs 1, 2, whereby the charge current induces a voltage drop in the resistors 3, 4 to cause the RS latch to malfunction. NOT circuits 8, 11 and a NOR circuit 13 transmit a regular on signal, while NOT circuits 9, 12 and a NOR circuit 14 transmit a regular off signal.

Abstract: A level shift circuit applies an on signal 25 and an off signal 26 each consisting of pulses, to high-voltage MOSFETs 1, 2, respectively, having their source connected to a common potential COM to induce a voltage drop in load resistors 3, 4 in order to set or reset a RS latch 15 to turn on or off an IGBT 17 on an upper arm of a PWM inverter bridge circuit having a varying emitter potential, a circuit free from a long time delay prevents an increase dV/dt in potential of an AC output terminal OUT that results in charging of a capacity between a source and a drain of each of the high-voltage MOSFETs 1, 2, whereby the charge current induces a voltage drop in the resistors 3, 4 to cause the RS latch to malfunction. NOT circuits 8, 11 and a NOR circuit 13 transmit a regular on signal, while NOT circuits 9, 12 and a NOR circuit 14 transmit a regular off signal.

Abstract: A high voltage integrated circuit is provided that includes a first region of first conductivity type; a second region of second conductivity type formed in a first major surface of the first region; a third region of first conductivity type formed in a selected area of a surface of the second region; first source region and first drain region of the first conductivity type formed in the second region, apart from the third region; a first gate electrode formed on a surface of the second region between the first source region and first drain region, through an insulating film; second source region and second drain region of second conductivity type formed in a surface of the third region; and a second gate electrode formed on a surface of the third region between the second source region and the second drain region, through an insulating film.

Abstract: A high voltage integrated circuit is provided that includes a first region of first conductivity type; a second region of second conductivity type formed in a first major surface of the first region; a third region of first conductivity type formed in a selected area of a surface of the second region; first source region and first drain region of the first conductivity type formed in the second region, apart from the third region; a first gate electrode formed on a surface of the second region between the first source region and first drain region, through an insulating film; second source region and second drain region of second conductivity type formed in a surface of the third region; and a second gate electrode formed on a surface of the third region between the second source region and the second drain region, through an insulating film.

Abstract: The operating characteristics of emitter-switched thyristors (1) are improved by the addition of a floating ohmic contact (14) over adjacent regions of n+ and p+ type (15,16). In a lateral device, the floating ohmic contact (14) and the adjacent regions of n+ and p+ type (15,16) are provided between the anode region (4) and the cathode region (8,9,10). The device has enhanced turn-on characteristics with a high breakdown voltage and high current density capabilities.

Abstract: A level shift circuit includes first and second operation circuits, a bias circuit, and a current control circuit. The first and second operation circuits include high-voltage transistors and low-voltage transistors connected in series. The high-voltage transistors are controlled according to a potential at the interconnection point between the low-voltage and high-voltage transistors of opposite operation circuits. The bias circuit is provided in a one-to-one correspondence with the operation circuits and connected to the low-voltage transistors in series to activate the transistors in the stationary on state and decrease currents flowing into the transistors to a stationary current. The current control circuit connects to the bias circuit in parallel to increase the currents just after the low-level transistors are turned on to a high peak current. The low-voltage transistors are turned on/off alternately in response to the state transition of an input signal.