Patents by Inventor Naoki Makita
Naoki Makita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20030193052Abstract: A barrier layer that meets three requirements, “withstand well against etching and protect a semiconductor film from an etchant as an etching stopper”, “allow impurities to move in itself during heat treatment for gettering”, and “have excellent reproducibility”, is formed and used to getter impurities contained in a semiconductor film. The barrier layer is a silicon oxide film and the ratio of a sub-oxide contained in the barrier layer is 18% or higher.Type: ApplicationFiled: March 28, 2003Publication date: October 16, 2003Applicant: Semiconductor Energy Laboratory Co. Ltd.Inventors: Misako Nakazawa, Mitsuhiro Ichijo, Toshiji Hamatani, Hideto Ohnuma, Naoki Makita
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Publication number: 20030173566Abstract: A catalytic element is added to an amorphous semiconductor film and heat treatment is conducted therefor to produce a crystalline semiconductor film with good quality, a TFT (semiconductor device) with a satisfactory characteristic is realized using the crystalline semiconductor film. A semiconductor layer includes a region containing an impurity element which has a concentration of 1×1019/cm3 to 1×1021/cm3 and belongs to group 15 of the periodic table and an impurity element which has a concentration of 1.5×1019/cm3 to 3×1021/cm3 and belongs to group 13 of the periodic table, and the region is a region to which a catalytic element left in the semiconductor film (particularly, the channel forming region) moves.Type: ApplicationFiled: February 13, 2003Publication date: September 18, 2003Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Misako Nakazawa, Naoki Makita
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Publication number: 20030089909Abstract: By adding a novel improvement to the technique disclosed in JP 8-78329 A, a manufacturing method in which film characteristics of a semiconductor film having a crystalline structure are improved is provided. In addition, a TFT having superior TFT characteristics, such as field effect mobility, which uses the semiconductor film as an active layer, and a method of manufacturing the TFT, are also provided. A metallic element which promotes the crystallization of silicon is added to a semiconductor film having an amorphous structure and an oxygen concentration within the film of less than 5×1018/cm3. The semiconductor film having an amorphous structure is then heat-treated, forming a semiconductor film having a crystalline structure. Subsequently, an oxide film on the surface is removed. Oxygen is introduced to the semiconductor film having a crystalline structure, and processing is performed such that the concentration of oxygen within the film is from 5×1018/cm3 to 1×1021/cm3.Type: ApplicationFiled: October 8, 2002Publication date: May 15, 2003Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hidekazu Miyairi, Aiko Shiga, Katsumi Nomura, Naoki Makita, Takuya Matsuo
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Publication number: 20030089911Abstract: A semiconductor device which has satisfactory characteristics is provided. The semiconductor device includes a TFT manufactured by using a satisfactory crystalline semiconductor film and a circuit manufactured by using the TFT. An n-type impurity element (typically, phosphorous) is added to a gettering region of an n-channel TFT. A p-type impurity element (typically, boron) and a rare gas element (typically, argon) are added to a gettering region of a p-channel TFT. Then, there is performed heat treatment for gettering a catalytic element that remains in a semiconductor film.Type: ApplicationFiled: August 26, 2002Publication date: May 15, 2003Inventors: Kenji Kasahara, Naoki Makita, Takuya Matsuo
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Publication number: 20030067004Abstract: A spin addition method for catalyst elements is simple and very important technique, because the minimum amount of a catalyst element necessary for crystallization can be easily added by controlling the catalyst element concentration within a catalyst element solution, but there is a problem in that uniformity in the amount of added catalyst element within a substrate is poor. The non-uniformity in the amount of added catalyst element within the substrate is thought to influence fluctuation in crystallinity of a crystalline semiconductor film that has undergone thermal crystallization, and exert a bad influence on the electrical characteristics of TFTs finally structured by the crystalline semiconductor film. The present invention solves this problem with the aforementioned conventional technique.Type: ApplicationFiled: August 28, 2002Publication date: April 10, 2003Inventors: Misako Nakazawa, Toshiji Hamatani, Naoki Makita
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Publication number: 20030062546Abstract: In a TFT with a GOLD structure, there is provided a structure which is able to improve an operating characteristic and reliability and reduce an off current value in order to reduce power consumption of a semiconductor device. The surface of LDD region (4) overlapped with a portion (7a) of a gate electrode through a gate insulating film (6) interposed therebetween is extremely flattened. Thus, it is possible to obtain a TFT structure which is capable of reducing a parasitic capacitance in the LDD region of the TFT with the GOLD structure, reducing an off current value, improving reliability, and enabling high speed operation.Type: ApplicationFiled: September 26, 2002Publication date: April 3, 2003Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takashi Hamada, Hidekazu Miyairi, Takuya Matsuo, Naoki Makita, Katsumi Nomura
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Publication number: 20030032267Abstract: The invention is directed to a countermeasure against a local amorphous region observed as an eddy pattern on a thermally crystallized crystalline silicon film. The local amorphous region is thought to result from a deficiently formed ultra-thin silicon oxide film by ozone water treatment, which causes a local phenomenon of repelling a catalyst element solution during spin coating. This inhibits a uniform addition of a catalyst element. A relationship between an ozone concentration of ozone water and a wait time between the ozone water treatment and the subsequent step of adding the catalyst element is deduced and used for planning the countermeasure against the local amorphous region.Type: ApplicationFiled: August 1, 2002Publication date: February 13, 2003Applicant: Semiconductor Energy Laboratoy Co., Ltd.Inventors: Toshiji Hamatani, Misako Nakazawa, Naoki Makita
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Publication number: 20030025158Abstract: Problems in prior art regarding an n-channel TFT in the source/drain gettering method are solved. In the n-channel TFT, its source/drain regions contain only an n-type impurity. Therefore, compared to a p-channel TFT whose source/drain regions contain an n-type impurity and a higher concentration of p-type impurity, the gettering efficiency is inferior in a channel region of the n-channel transistor. Accordingly, the problem of inferior gettering efficiency in the n-channel TFT can be solved by providing at an end of its source/drain regions a highly efficient gettering region that contains an n-type impurity and a p-type impurity both with the concentration of the p-type impurity set higher than the concentration of the n-type impurity.Type: ApplicationFiled: June 27, 2002Publication date: February 6, 2003Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Naoki Makita, Misako Nakazawa, Hideto Ohnuma, Takuya Matsuo
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Publication number: 20020173085Abstract: A technique for manufacturing TFTs having little dispersion in their electrical characteristics is provided. Contamination of a semiconductor film is reduced by performing oxidation processing having an organic matter removing effect, forming a clean oxide film, after removing a natural oxide film formed on a semiconductor film surface. TFTs having little dispersion in their electrical characteristics can be obtained by using the semiconductor film thus obtained in active layers of the TFTs, and the electrical properties can be improved. In addition, deterioration in productivity and throughput can be reduced to a minimum by using a semiconductor manufacturing apparatus of the present invention.Type: ApplicationFiled: April 29, 2002Publication date: November 21, 2002Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD. & SHARP KABUSHIKI KAISHAInventors: Setsuo Nakajima, Aiko Shiga, Naoki Makita, Takuya Matsuo
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Publication number: 20020053674Abstract: A catalytic element for promoting crystallization of an amorphous silicon film is efficiently gettered to provide a highly reliable TFT, and an electro-optical device using the TFT and a method of manufacturing the electro-optical device are provided. The electro-optical device has an n-channel TFT and a p-channel TFT. A semiconductor layer of the p-channel TFT has a channel forming region (13), a region (11) containing an n-type impurity element and a p-type impurity element, and a region (12) containing only a p-type impurity element. In the p-channel TFT, a wiring line for electrically connecting the TFTs is connected to the region (12) containing only a p-type impurity element. The region containing an n-type impurity element in the p-channel TFT is narrower than a region doped with an n-type impurity element in a semiconductor layer of the n-channel TFT.Type: ApplicationFiled: November 2, 2001Publication date: May 9, 2002Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Setsuo Nakajima, Hideto Ohnuma, Naoki Makita, Takuya Matsuo
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Publication number: 20010025992Abstract: To manufacture a liquid crystal display device with high thin film transistor accumulation, high productivity and high reliability by efficiently gettering a catalyst element, which promotes crystallization of an amorphous silicon film, from a channel region. In order to solve the above object, a step of providing a gettering sink on the outside of a p-channel thin film transistor region, and a step of removing a region provided on the outside of the thin film transistor region within the region where the catalyst element is gettered in a self-aligning manner by a source wiring or a drain wiring, are combined.Type: ApplicationFiled: April 2, 2001Publication date: October 4, 2001Inventors: Setsuo Nakajima, Naoki Makita
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Publication number: 20010021544Abstract: In a crystallization process of an amorphous semiconductor film, a first crystalline semiconductor film having crystalline regions, and dotted with amorphous regions within the crystalline regions, is obtained by performing heat treatment processing after introducing a metallic element which promotes crystallization on the amorphous semiconductor film. The amorphous regions are kept within a predetermined range by regulating the heat treatment conditions at this point. Laser annealing is performed on the first crystalline semiconductor film, to form a second crystalline semiconductor film. Electrical characteristics for a TFT manufactured based on the second crystalline semiconductor film can be obtained having less dispersion.Type: ApplicationFiled: March 5, 2001Publication date: September 13, 2001Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hideto Ohnuma, Chiho Kokubo, Koichiro Tanaka, Naoki Makita, Shuhei Tsuchimoto
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Patent number: 6162667Abstract: In a fabrication of a semiconductor device, an amorphous semiconductor film is first formed on a substrate having an insulating surface. Then, a minute amount of catalyst elements for accelerating crystallization of the amorphous semiconductor film is supplied to at least a portion of a surface of the amorphous semiconductor film. A heat treatment is further conducted so that the supplied catalyst elements are diffused into the amorphous semiconductor film. Thus, the catalyst elements are introduced uniformly into the amorphous semiconductor film in a very minute amount or at a low concentration, resulting in polycrystallization of at least a portion of the amorphous semiconductor film. Utilizing the thus obtained crystalline semiconductor film on the substrate surface as an active region, a semiconductor device such as a TFT is fabricated.Type: GrantFiled: March 23, 1995Date of Patent: December 19, 2000Assignee: Sharp Kabushiki KaishaInventors: Takashi Funai, Naoki Makita, Yoshitaka Yamamoto, Tadayoshi Miyamoto, Takamasa Kousai, Masashi Maekawa
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Patent number: 6013544Abstract: A method for fabricating a semiconductor device including an active region obtained by utilizing a silicon semiconductor film having crystallinity which is formed on an insulating substrate is disclosed. A crystalline silicon semiconductor film is obtained by introducing catalyst elements for promoting the crystallization into a lower amorphous silicon semiconductor film and then performing a heat treatment onto the lower amorphous silicon semiconductor film. Thereafter, an upper amorphous silicon semiconductor film is formed on the obtained lower crystalline silicon semiconductor film, which is subsequently subjected to a heat treatment so as to obtain an upper crystalline silicon semiconductor film. Then, the upper crystalline silicon semiconductor film is removed. By this process, the catalyst elements remaining in the lower crystalline silicon semiconductor film moves into the upper crystalline silicon semiconductor film.Type: GrantFiled: March 4, 1996Date of Patent: January 11, 2000Assignee: Sharp Kabushiki KaishaInventors: Naoki Makita, Tadayoshi Miyamoto, Tsukasa Shibuya
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Patent number: 5981974Abstract: A semiconductor device includes a plurality of thin film transistors on a substrate having an insulating surface. A channel region of the thin film transistor comprises a crystalline Si film crystallized by a successive irradiation with a pulse laser beam in a scanning pitch P. A size Xs of the channel region in the scanning direction of the pulse laser beam and the scanning pitch P of the pulse laser beam have a relationship approximately equal to Xs=nP where n is an integer of 1 or more.Type: GrantFiled: September 22, 1997Date of Patent: November 9, 1999Assignee: Sharp Kabushiki KaishaInventor: Naoki Makita
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Patent number: 5975258Abstract: A damping force control type hydraulic shock absorber of the present invention includes a cylindrical valve member. One end of the cylinder valve member is closed. Also, the shock absorber includes annular inner and outer seal portions, and a valve seat provided there-between, all of which project from an inner wall of a bottom portion of the valve member and are concentric with one another. A disk valve is secured at an inner peripheral portion thereof to the inner seal portion and abuts at an outer peripheral portion thereof on the valve seat. A retainer disk stacks on the disk valve. An annular seal ring abuts at an inner peripheral portion thereof of an outer peripheral edge portion of the retainer disk, and is secured at an outer peripheral portion thereof to the outer seal portion. A blocking member is connected to an open end of the valve member so that a pilot chamber is formed by the retainer disk, the seal ring and the blocking member.Type: GrantFiled: November 7, 1997Date of Patent: November 2, 1999Assignee: Tokico, LtdInventors: Takashi Nezu, Naoki Makita
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Patent number: 5970327Abstract: A semiconductor device comprising a substrate having thereon an amorphous silicon film fabricated by a reduced pressure chemical vapor deposition, characterized in that a thin film transistor is provided by using a crystalline silicon film obtained by effecting crystal growth in parallel with the surface of the substrate at the periphery of a region containing a selectively introduced metallic element, the region being obtained by selectively introducing a metallic element capable of accelerating the crystallization of the amorphous silicon film and heating the region thereafter.Type: GrantFiled: November 21, 1997Date of Patent: October 19, 1999Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Naoki Makita, Takashi Funai, Toru Takayama
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Patent number: 5934421Abstract: In a damping force control type hydraulic shock absorber, the flow path area of a port is changed by moving a spool according to an electric current supplied to an actuator, and thus the flow path area of a passage between cylinder upper and lower chambers is directly changed, thereby controlling orifice characteristics. Moreover, the pressure in a pilot chamber is changed according to the resulting pressure loss so as to change the valve opening pressure of a disk valve, thereby controlling valve characteristics. This enables the damping force characteristic control range to be widened. The pilot chamber is formed by the side wall of a valve member, the disk valve, a seal disk, and a seal member, also, the seal member has no sliding portion. It is therefore possible to minimize the leakage of hydraulic fluid and to obtain stable damping force characteristics. It is also possible to minimize variations in damping force with temperature changes.Type: GrantFiled: December 11, 1996Date of Patent: August 10, 1999Assignee: Tokico Ltd.Inventors: Takao Nakadate, Akira Kashiwagi, Takashi Nezu, Naoki Makita
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Patent number: 5936291Abstract: The thin film transistor of this invention is formed on a substrate and includes an active layer and a first insulating film and a second insulating film sandwiching the active layer, wherein the overall polarity of fixed charges contained in the first insulating film is the reverse of the overall polarity of fixed charges contained in the second insulating film.Type: GrantFiled: January 30, 1998Date of Patent: August 10, 1999Assignee: Sharp Kabushiki KaishaInventors: Naoki Makita, Muneyuki Motohashi, Hidehiko Yamashita, Hideo Izawa
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Patent number: 5851860Abstract: The semiconductor device of the invention includes: a substrate having an insulating surface; an active region formed on the insulating surface of the substrate, the active region being formed by a crystalline silicon film; and an insulating thin film formed on the active region. In the semiconductor device, the active region contains a catalyst element for promoting a crystallization of an amorphous silicon film by a heat treatment.Type: GrantFiled: June 2, 1995Date of Patent: December 22, 1998Assignee: Sharp Kabushiki KaishaInventors: Naoki Makita, Takashi Funai