Patents by Inventor Naoki Matsunaga
Naoki Matsunaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200393019Abstract: A driving apparatus 100 includes a motor 20 that generates drive power and power transmission units 30, 40, and 50 that transmit drive power of the motor 20 to an output shaft 60. The power transmission units 30, 40, and 50 include a brake mechanism 40 that brakes rotation of the output shaft 60 and a deceleration mechanism 50 that converts a torque of the motor 20, and transmits a resultant to the output shaft 60, and the brake mechanism 40 is arranged at a part before the deceleration mechanism 50, and the deceleration mechanism 50 is arranged at a part before the output shaft 60.Type: ApplicationFiled: August 27, 2020Publication date: December 17, 2020Applicant: HONDA MOTOR CO., LTD.Inventors: Naoki Matsunaga, Tsuyoshi Yoshigasaki, Kenta Kohigashi
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Publication number: 20200393011Abstract: A driving apparatus 100 includes a motor 20 that generates drive power and power transmission units 30, 40, and 50 that transmit drive power of the motor 20 to an output shaft 60. The power transmission units 30, 40, and 50 include at least one of a clutch mechanism 30 that switches between a state where the motor 20 and the output shaft 60 are connected and a state where the motor 20 and the output shall 60 are disconnected, in accordance with movement of an operation rod 32, and a brake mechanism 40 that brakes rotation of the output shaft 60 in accordance with movement of an operation rod 43.Type: ApplicationFiled: August 27, 2020Publication date: December 17, 2020Applicant: HONDA MOTOR CO., LTD.Inventors: Naoki Matsunaga, Tsuyoshi Yoshigasaki, Kenta Kohigashi
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Publication number: 20200393012Abstract: A driving apparatus 100 includes a motor 20 that generates drive power and power transmission units 30, 40, and 50 that transmit drive power of the motor 20 to an output shaft 60. The power transmission units 30, 40, and 50 include a clutch mechanism 30 that switches between a state where the motor 20 and the output shaft 60 are connected and a state where the motor 20 and the output shaft 60 are disconnected, and a brake mechanism 40 that brakes rotation of the output shaft 60, and the clutch mechanism 30 is arranged so as to overlap the brake mechanism 40 in a radial direction.Type: ApplicationFiled: August 27, 2020Publication date: December 17, 2020Applicant: HONDA MOTOR CO., LTD.Inventors: Naoki Matsunaga, Tsuyoshi Yoshigasaki, Kenta Kohigashi
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Publication number: 20200381062Abstract: According to one embodiment, there is provided a non-volatile semiconductor storage device including a non-volatile memory, a monitoring section, a determining section, and a notification processing section. The non-volatile memory includes a plurality of memory cells driven by word lines and a voltage generating section that generates a read voltage to be applied to the word lines. The monitoring section monitors a change in a threshold distribution of the plurality of memory cells upon performing a read processing to read data from the plurality of memory cells by applying the read voltage to the word lines. The determining section determines a degree of deterioration of the non-volatile memory in accordance with a monitoring result by the monitoring section. The notification processing section notifies a life of the non-volatile memory in accordance with a determining result by the determining section.Type: ApplicationFiled: August 19, 2020Publication date: December 3, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventor: Naoki MATSUNAGA
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Publication number: 20200355243Abstract: There is provided with a speed reduction mechanism. An output shaft is arranged on the same axis as an input shaft. A plurality of gears transmit a driving force input to the input shaft to the output shaft. The plurality of gears include an input gear provided on the input shaft, an output gear provided on the output shaft, and a plurality of transmission gears arranged side by side in a circumferential direction of the input shaft.Type: ApplicationFiled: July 24, 2020Publication date: November 12, 2020Applicant: HONDA MOTOR CO., LTD.Inventors: Tsuyoshi Yoshigasaki, Kenta Kohigashi, Naoki Matsunaga
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Patent number: 10762969Abstract: According to one embodiment, there is provided a non-volatile semiconductor storage device including a non-volatile memory, a monitoring section, a determining section, and a notification processing section. The non-volatile memory includes a plurality of memory cells driven by word lines and a voltage generating section that generates a read voltage to be applied to the word lines. The monitoring section monitors a change in a threshold distribution of the plurality of memory cells upon performing a read processing to read data from the plurality of memory cells by applying the read voltage to the word lines. The determining section determines a degree of deterioration of the non-volatile memory in accordance with a monitoring result by the monitoring section. The notification processing section notifies a life of the non-volatile memory in accordance with a determining result by the determining section.Type: GrantFiled: March 15, 2019Date of Patent: September 1, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventor: Naoki Matsunaga
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Patent number: 10443110Abstract: A high toughness and high tensile strength thick steel plate has a plate thickness of 100 mm or more, wherein a reduction of area in a center of the plate thickness by tension in a plate thickness direction is 40% or more. Thus, a high tensile strength thick steel plate with excellent strength and toughness in a center of the plate thickness can be obtained with no need for a larger production line, even in the case of producing a high strength thick steel plate for which the addition amount of alloying element needs to be increased.Type: GrantFiled: September 9, 2014Date of Patent: October 15, 2019Assignee: JFE Steel CorporationInventors: Shigeki Kitsuya, Katsuyuki Ichimiya, Kazukuni Hase, Teruhisa Kinugawa, Naoki Matsunaga, Kenji Hayashi, Masayuki Horie, Yusuke Terazawa, Shigeru Endo
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Publication number: 20190214097Abstract: According to one embodiment, there is provided a non-volatile semiconductor storage device including a non-volatile memory, a monitoring section, a determining section, and a notification processing section. The non-volatile memory includes a plurality of memory cells driven by word lines and a voltage generating section that generates a read voltage to be applied to the word lines. The monitoring section monitors a change in a threshold distribution of the plurality of memory cells upon performing a read processing to read data from the plurality of memory cells by applying the read voltage to the word lines. The determining section determines a degree of deterioration of the non-volatile memory in accordance with a monitoring result by the monitoring section. The notification processing section notifies a life of the non-volatile memory in accordance with a determining result by the determining section.Type: ApplicationFiled: March 15, 2019Publication date: July 11, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventor: Naoki MATSUNAGA
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Publication number: 20190207469Abstract: A driving device includes a motor unit including a motor, and a speed reducer attached to the motor unit. The speed reducer includes a plurality of gears combined to decelerate an output of the motor, and a gear case configured to support the plurality of gears and attached to the motor unit. The gear case is selected from a plurality of types of gear cases. The plurality of types of gear cases are different from one another in an arrangement of the plurality of gears and a position of an output shaft relative to an input shaft.Type: ApplicationFiled: December 5, 2018Publication date: July 4, 2019Inventors: Kenta KOHIGASHI, Tsuyoshi YOSHIGASAKI, Naoki MATSUNAGA
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Patent number: 10269436Abstract: According to one embodiment, there is provided a non-volatile semiconductor storage device including a non-volatile memory, a monitoring section, a determining section, and a notification processing section. The non-volatile memory includes a plurality of memory cells driven by word lines and a voltage generating section that generates a read voltage to be applied to the word lines. The monitoring section monitors a change in a threshold distribution of the plurality of memory cells upon performing a read processing to read data from the plurality of memory cells by applying the read voltage to the word lines. The determining section determines a degree of deterioration of the non-volatile memory in accordance with a monitoring result by the monitoring section. The notification processing section notifies a life of the non-volatile memory in accordance with a determining result by the determining section.Type: GrantFiled: March 12, 2018Date of Patent: April 23, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventor: Naoki Matsunaga
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Publication number: 20180204623Abstract: According to one embodiment, there is provided a non-volatile semiconductor storage device including a non-volatile memory, a monitoring section, a determining section, and a notification processing section. The non-volatile memory includes a plurality of memory cells driven by word lines and a voltage generating section that generates a read voltage to be applied to the word lines. The monitoring section monitors a change in a threshold distribution of the plurality of memory cells upon performing a read processing to read data from the plurality of memory cells by applying the read voltage to the word lines. The determining section determines a degree of deterioration of the non-volatile memory in accordance with a monitoring result by the monitoring section. The notification processing section notifies a life of the non-volatile memory in accordance with a determining result by the determining section.Type: ApplicationFiled: March 12, 2018Publication date: July 19, 2018Applicant: Toshiba Memory CorporationInventor: Naoki Matsunaga
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Patent number: 10000833Abstract: A thick, high-toughness high-strength steel plate has excellent strength and toughness in the central area through the plate thickness. The thick steel plate has a specific chemical composition and includes a microstructure having, throughout an entire region in the plate thickness direction, an average prior austenite grain size of not more than 50 ?m and a martensite and/or bainite phase area fraction of not less than 80%. A continuously cast slab having the specific chemical composition is heated to 1200° C. to 1350° C., hot worked with a strain rate of not more than 3/s and a cumulative working reduction of not less than 15%, and thereafter hot rolled and heat treated.Type: GrantFiled: March 11, 2014Date of Patent: June 19, 2018Assignee: JFE STEEL CORPORATIONInventors: Shigeki Kitsuya, Naoki Matsunaga, Katsuyuki Ichimiya, Kazukuni Hase, Shigeru Endo
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Patent number: 9953716Abstract: According to one embodiment, there is provided a non-volatile semiconductor storage device including a non-volatile memory, a monitoring section, a determining section, and a notification processing section. The non-volatile memory includes a plurality of memory cells driven by word lines and a voltage generating section that generates a read voltage to be applied to the word lines. The monitoring section monitors a change in a threshold distribution of the plurality of memory cells upon performing a read processing to read data from the plurality of memory cells by applying the read voltage to the word lines. The determining section determines a degree of deterioration of the non-volatile memory in accordance with a monitoring result by the monitoring section. The notification processing section notifies a life of the non-volatile memory in accordance with a determining result by the determining section.Type: GrantFiled: April 28, 2017Date of Patent: April 24, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventor: Naoki Matsunaga
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Publication number: 20170236593Abstract: According to one embodiment, there is provided a non-volatile semiconductor storage device including a non-volatile memory, a monitoring section, a determining section, and a notification processing section. The non-volatile memory includes a plurality of memory cells driven by word lines and a voltage generating section that generates a read voltage to be applied to the word lines. The monitoring section monitors a change in a threshold distribution of the plurality of memory cells upon performing a read processing to read data from the plurality of memory cells by applying the read voltage to the word lines. The determining section determines a degree of deterioration of the non-volatile memory in accordance with a monitoring result by the monitoring section. The notification processing section notifies a life of the non-volatile memory in accordance with a determining result by the determining section.Type: ApplicationFiled: April 28, 2017Publication date: August 17, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Naoki MATSUNAGA
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Patent number: 9666299Abstract: According to one embodiment, there is provided a non-volatile semiconductor storage device including a non-volatile memory, a monitoring section, a determining section, and a notification processing section. The non-volatile memory includes a plurality of memory cells driven by word lines and a voltage generating section that generates a read voltage to be applied to the word lines. The monitoring section monitors a change in a threshold distribution of the plurality of memory cells upon performing a read processing to read data from the plurality of memory cells by applying the read voltage to the word lines. The determining section determines a degree of deterioration of the non-volatile memory in accordance with a monitoring result by the monitoring section. The notification processing section notifies a life of the non-volatile memory in accordance with a determining result by the determining section.Type: GrantFiled: September 6, 2016Date of Patent: May 30, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Naoki Matsunaga
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Publication number: 20170088913Abstract: A high toughness and high tensile strength thick steel plate has a plate thickness of 100 mm or more, wherein a reduction of area in a center of the plate thickness by tension in a plate thickness direction is 40% or more. Thus, a high tensile strength thick steel plate with excellent strength and toughness in a center of the plate thickness can be obtained with no need for a larger production line, even in the case of producing a high strength thick steel plate for which the addition amount of alloying element needs to be increased.Type: ApplicationFiled: September 9, 2014Publication date: March 30, 2017Applicant: JFE STEEL CORPORATIONInventors: Shigeki Kitsuya, Katsuyuki Ichimiya, Kazukuni Hase, Teruhisa Kinugawa, Naoki Matsunaga, Kenji Hayashi, Masayuki Horie, Yusuke Terazawa, Shigeru Endo
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Publication number: 20160372209Abstract: According to one embodiment, there is provided a non-volatile semiconductor storage device including a non-volatile memory, a monitoring section, a determining section, and a notification processing section. The non-volatile memory includes a plurality of memory cells driven by word lines and a voltage generating section that generates a read voltage to be applied to the word lines. The monitoring section monitors a change in a threshold distribution of the plurality of memory cells upon performing a read processing to read data from the plurality of memory cells by applying the read voltage to the word lines. The determining section determines a degree of deterioration of the non-volatile memory in accordance with a monitoring result by the monitoring section. The notification processing section notifies a life of the non-volatile memory in accordance with a determining result by the determining section.Type: ApplicationFiled: September 6, 2016Publication date: December 22, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Naoki MATSUNAGA
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Patent number: 9466370Abstract: According to one embodiment, there is provided a non-volatile semiconductor storage device including a non-volatile memory, a monitoring section, a determining section, and a notification processing section. The non-volatile memory includes a plurality of memory cells driven by word lines and a voltage generating section that generates a read voltage to be applied to the word lines. The monitoring section monitors a change in a threshold distribution of the plurality of memory cells upon performing a read processing to read data from the plurality of memory cells by applying the read voltage to the word lines. The determining section determines a degree of deterioration of the non-volatile memory in accordance with a monitoring result by the monitoring section. The notification processing section notifies a life of the non-volatile memory in accordance with a determining result by the determining section.Type: GrantFiled: July 15, 2014Date of Patent: October 11, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Naoki Matsunaga
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Patent number: 9390000Abstract: A memory device includes a substrate, a plurality of nonvolatile memory chips disposed on the substrate, and a memory controller disposed on the substrate. The memory chips may be disposed on the same side or the opposite side of the substrate as the memory controller. The memory controller controls each of the nonvolatile memory chips based on a firmware, where the firmware is written in a nonvolatile memory chip positioned at a location farthest from the memory controller. A write system may perform writing using a binary or single level cell (SLC) recording system in memory chips located closest to the memory controller and a multi-value or multi-level cell (MLC) recording system in memory chips located farthest from the memory controller. A weighting factor may be assigned for each of the nonvolatile memory chips based on the distance from the memory controller.Type: GrantFiled: January 16, 2013Date of Patent: July 12, 2016Assignee: Kabushiki Kaisha ToshibaInventor: Naoki Matsunaga
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Patent number: 9355685Abstract: A multi-chip package includes a first group of memory chips that includes a first memory chip and a second memory chip, a second group of memory chips that includes at least one memory chip, a first internal wiring system that couples the first memory chip and the second memory chip to a first terminal configured to receive a chip-enable signal, a second internal wiring system that couples the at least one memory chip to a second terminal configured to receive the chip-enable signal. The first memory chip and the second memory chip each include a chip address memory region configured to store an address associated with the memory chip, and an address rewrite module configured to rewrite the address associated with the memory chip and stored in the chip address memory region in response to an external operation.Type: GrantFiled: January 6, 2015Date of Patent: May 31, 2016Assignee: Kabushiki Kaisha ToshibaInventor: Naoki Matsunaga