Abstract: A thick, high-toughness high-strength steel plate has excellent strength and toughness in the central area through the plate thickness. The thick steel plate has a specific chemical composition and includes a microstructure having, throughout an entire region in the plate thickness direction, an average prior austenite grain size of not more than 50 ?m and a martensite and/or bainite phase area fraction of not less than 80%. A continuously cast slab having the specific chemical composition is heated to 1200° C. to 1350° C., hot worked with a strain rate of not more than 3/s and a cumulative working reduction of not less than 15%, and thereafter hot rolled and heat treated.

Abstract: Electrons are introduced to a cathode (1) side of a cell (10) to promote the reduction of carbon dioxide. On the other hand, the oxidation of methane is promoted in an anode (2) side by an oxide ion transported via a porous GDC electrolyte (3). When carbon monoxide and an oxide ion are generated, they are transported to the anode (2) together with methane gas to generate carbon monoxide and hydrogen. In addition, Cu and an oxide ion are reacted in the anode (2) to promote the oxidation of methane gas.

Abstract: A multi-chip package includes a first group of memory chips that includes a first memory chip and a second memory chip, a second group of memory chips that includes at least one memory chip, a first internal wiring system that couples the first memory chip and the second memory chip to a first terminal configured to receive a chip-enable signal, a second internal wiring system that couples the at least one memory chip to a second terminal configured to receive the chip-enable signal. The first memory chip and the second memory chip each include a chip address memory region configured to store an address associated with the memory chip, and an address rewrite module configured to rewrite the address associated with the memory chip and stored in the chip address memory region in response to an external operation.

Abstract: A multi-chip package includes a first group of memory chips that includes a first memory chip and a second memory chip, a second group of memory chips that includes at least one memory chip, a first internal wiring system that couples the first memory chip and the second memory chip to a first terminal configured to receive a chip-enable signal, a second internal wiring system that couples the at least one memory chip to a second terminal configured to receive the chip-enable signal. The first memory chip and the second memory chip each include a chip address memory region configured to store an address associated with the memory chip, and an address rewrite module configured to rewrite the address associated with the memory chip and stored in the chip address memory region in response to an external operation.

Abstract: According to one embodiment, there is provided a non-volatile semiconductor storage device including a non-volatile memory, a monitoring section, a determining section, and a notification processing section. The non-volatile memory includes a plurality of memory cells driven by word lines and a voltage generating section that generates a read voltage to be applied to the word lines. The monitoring section monitors a change in a threshold distribution of the plurality of memory cells upon performing a read processing to read data from the plurality of memory cells by applying the read voltage to the word lines. The determining section determines a degree of deterioration of the non-volatile memory in accordance with a monitoring result by the monitoring section. The notification processing section notifies a life of the non-volatile memory in accordance with a determining result by the determining section.

Abstract: According to one embodiment, there is provided a non-volatile semiconductor storage device including a non-volatile memory, a monitoring section, a determining section, and a notification processing section. The non-volatile memory includes a plurality of memory cells driven by word lines and a voltage generating section that generates a read voltage to be applied to the word lines. The monitoring section monitors a change in a threshold distribution of the plurality of memory cells upon performing a read processing to read data from the plurality of memory cells by applying the read voltage to the word lines. The determining section determines a degree of deterioration of the non-volatile memory in accordance with a monitoring result by the monitoring section. The notification processing section notifies a life of the non-volatile memory in accordance with a determining result by the determining section.

Abstract: According to one embodiment, a memory system according to one embodiment is equipped with several nonvolatile memory chips and a memory controller that controls the nonvolatile memory chips based on a firmware. The firmware is written in a nonvolatile memory chip positioned the farthest distance from the memory controller.

Abstract: A multi-chip package includes a first group of memory chips that includes a first memory chip and a second memory chip, a second group of memory chips that includes at least one memory chip, a first internal wiring system that couples the first memory chip and the second memory chip to a first terminal configured to receive a chip-enable signal, a second internal wiring system that couples the at least one memory chip to a second terminal configured to receive the chip-enable signal. The first memory chip and the second memory chip each include a chip address memory region configured to store an address associated with the memory chip, and an address rewrite module configured to rewrite the address associated with the memory chip and stored in the chip address memory region in response to an external operation.

Abstract: According to an embodiment, a memory system includes a nonvolatile memory that stores system data into a first address, a first data verifying unit, an address selecting unit, a first data operating unit, a second data verifying unit and a second data operating unit. The first data verifying unit reads the system data from the first address and verifies the system data read from the first address. The address selecting unit selects a second address when a verification result is not good. The first data operating unit that copies the system data stored in the first address into the second address. The second data verifying unit that reads the system data copied into the second address and verifies the system data read from the second address. The second data operating unit that erases the system data stored in the first address when a verification result is good.

Abstract: According to one embodiment, there is provided a non-volatile semiconductor storage device including a non-volatile memory, a monitoring section, a determining section, and a notification processing section. The non-volatile memory includes a plurality of memory cells driven by word lines and a voltage generating section that generates a read voltage to be applied to the word lines. The monitoring section monitors a change in a threshold distribution of the plurality of memory cells upon performing a read processing to read data from the plurality of memory cells by applying the read voltage to the word lines. The determining section determines a degree of deterioration of the non-volatile memory in accordance with a monitoring result by the monitoring section. The notification processing section notifies a life of the non-volatile memory in accordance with a determining result by the determining section.

Abstract: A semiconductor device includes: a semiconductor substrate; and an insulating layer formed on at least a main surface of the semiconductor substrate; wherein a contact hole is formed at the insulating layer so as to expose the main surface of the semiconductor substrate through the insulating layer so that a cross section of the contact hole parallel to the main surface of the semiconductor substrate is shaped rectangularly.

Abstract: The present invention provides a crystal of a pharmaceutically acceptable salt of N-{2-chloro-4-[(6,7-dimethoxy-4-quinolyl)oxy]phenyl}-N?-(5-methyl-3-isoxazolyl) urea. This crystal of salt is usable for the therapy of a disease selected from the group consisting of tumors, diabetic retinopathy, chronic rheumatism, psoriasis, atherosclerosis, Kaposi's sarcoma, and exudation type age-related maculopathy, and has characteristics suitable for applications of oral pharmaceutical preparations.

Abstract: The present invention relates to a compound represented by formula (I): (wherein all the symbols have the same meanings as defined in the above description) and a production method and use thereof. The compounds represented by formula (I), or its salt, N-oxide or solvate, or a prodrug thereof have p38 MAP kinase inhibitory activity, and are useful in the prevention and/or treatment of those diseases that are supposedly caused or deteriorated by abnormal production of cytokines including inflammatory cytokine or chemokine, or by over response thereto, namely cytokine-mediated diseases such as inflammatory diseases, respiratory diseases, cardiovascular disease, central nervous system diseases, and the like.

Abstract: A light shielding film capable of shielding against light entering an active layer of a TFT and electroconductive is formed on the lower layer side of the active layer. Electrical stress is applied by causing a current in an insulating film between source and drain electrodes and the light shielding film to introduce a trap level at a density at least about 5×1012/cm2 into a source region and a drain region in a surface portion of the active layer on the light shielding film side.

Abstract: A thin film transistor is provided including an active layer, in which a source region and drain region are formed, a first light-shielding film shielding a light incident on the active layer, and a second light-shielding film between the active layer and the first shielding film. A carrier concentration of at least surface portion of the second light-shielding film which opposes the active layer is about 1017/cm3 or less.

Abstract: A method of fabricating a thin film transistor including an electrically insulating substrate, a semiconductor layer formed on the substrate, and source and drain electrodes formed above source and drain regions formed in the semiconductor layer, the source and drain electrodes being composed of aluminum or aluminum alloy, the method including the steps of forming a gate electrode, implanting impurity ions into the semiconductor layer for forming the source and drain regions, forming an interlayer insulating film entirely over the substrate, forming contact holes throughout the interlayer insulating film such that the source and drain regions are exposed through the contact holes, forming an electrically conductive film composed of aluminum or aluminum alloy, in the contact holes for forming the source and drain electrodes, and thermally annealing the substrate at 275 to 350 degrees centigrade for 1.5 to 3 hours in inert atmosphere.

Abstract: A thin-film semiconductor device is provided including a plurality of thin-film transistors (TFT) having different driving voltages formed on an glass substrate, wherein a gate insulator electric field at each of the driving voltages of the plurality of thin-film transistors is in a range of about 1 MV/cm to 2 MV/cm, and a drain concentration of p-type thin-film transistors (TFT) is in a range of about 3E+19/cm3 to 1E+20/cm3.

Abstract: The present invention provides a crystal of a pharmaceutically acceptable salt of N-{2-chloro-4-[(6,7-dimethoxy-4-quinolyl)oxy]phenyl}-N?-(5-methyl-3-isoxazolyl) urea. This crystal of salt is usable for the therapy of a disease selected from the group consisting of tumors, diabetic retinopathy, chronic rheumatism, psoriasis, atherosclerosis, Kaposi's sarcoma, and exudation type age-related maculopathy, and has characteristics suitable for applications of oral pharmaceutical preparations.

Abstract: A light shielding film capable of shielding against light entering an active layer of a TFT and electroconductive is formed on the lower layer side of the active layer. Electrical stress is applied by causing a current in an insulating film between source and drain electrodes and the light shielding film to introduce a trap level at a density at least about 5×1012/cm2 into a source region and a drain region in a surface portion of the active layer on the light shielding film side.

Abstract: A thin film transistor is provided including an active layer, in which a source region and drain region are formed, a first light-shielding film shielding a light incident on the active layer, and a second light-shielding film between the active layer and the first shielding film. A carrier concentration of at least surface portion of the second light-shielding film which opposes the active layer is about 1017/cm3 or less.