Patents by Inventor Naoki Nakagawa

Naoki Nakagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7791073
    Abstract: In first and second gate electrodes constituting a gate electrode, the gate length of the second gate electrode is set shorter than the gate length of the first gate electrode and short enough to produce the short channel effect. The threshold voltage of a second transistor corresponding to the second gate electrode can thereby be made lower than the threshold voltage of a first transistor corresponding to the first gate electrode. When the same voltage is applied to the first and second gate electrodes, an electric field concentration at the channel edge on the drain side is reduced. This in result reduces the channel length modulation effect.
    Type: Grant
    Filed: April 12, 2007
    Date of Patent: September 7, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hidetada Tokioka, Naoki Nakagawa, Masafumi Agari
  • Publication number: 20100133541
    Abstract: In accordance with an exemplary aspect of the present invention, a thin film transistor array substrate includes a transparent insulating substrate, and a thin film transistor for pixel switching and a thin film transistor for a drive circuit formed on the transparent insulating substrate, wherein the thin film transistor for a drive circuit includes an amorphous silicon film formed on the transparent insulating film, a microcrystalline silicon film formed on the amorphous silicon film, a first source electrode and a first drain electrode formed on the microcrystalline silicon film, the first source electrode and the first drain electrode being opposed with a first channel area interposed therebetween, a protective insulating film that covers the first source electrode and the first drain electrode, and an upper gate electrode formed so as to be opposed to the first channel area with the protective insulating film interposed therebetween.
    Type: Application
    Filed: December 1, 2009
    Publication date: June 3, 2010
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yusuke UCHIDA, Koji ODA, Naoki NAKAGAWA
  • Publication number: 20100130294
    Abstract: A method for fixing a boot includes mounting a tubular anchoring areas (12, 13), defined in opposite ends of a resinous boot (11), on an outer periphery of a counterpart member (1), and applying a clamping force to boot bands (15, 16) mounted around respective outer peripheries of the tubular anchoring areas (12, 13) to thereby fix the tubular anchoring areas (12, 13) to the outer periphery of the counterpart member (1). Coils (17) are disposed around respective outer peripheries of the boot bands (15, 16) to generate an induction current in the boot bands (15, 16). In this way, a reactive force of the magnetic field is generated between the coils (17) and the boot bands (15, 16) to plastically deform the boot bands (15, 16) and reduce their diameters, whereby the tubular anchoring areas (12, 13) are fixed to the outer periphery of the counterpart member (1).
    Type: Application
    Filed: July 25, 2008
    Publication date: May 27, 2010
    Applicant: NTN Corporation
    Inventor: Naoki Nakagawa
  • Publication number: 20100119300
    Abstract: Provided is an outer joint member for a constant velocity universal joint, which can be manufactured at low cost. The outer joint member includes a cup member (13) having a tubular body portion (1) and a bottom portion (12) for closing one opening of the body portion (1), and also includes a disc-like flange member (2) mounted on the bottom portion (12) of the cup member (13). A protrusion (8) is provided on the bottom portion (12), the flange member (2) is fitted on the protrusion (8), and an inside surface (4a) of the flange member (2) and an outer diameter surface (3) of the protrusion are bonded together by welding. In the welding, molten metal flows into a relief portion (9) provided in a fitting portion between the cup member (13) and the flange member (2), and this prevents the weld bead from raising, thereby reducing costs otherwise necessary to eliminate the raised bead.
    Type: Application
    Filed: March 7, 2008
    Publication date: May 13, 2010
    Inventors: Naoki Nakagawa, Yasuyuki Watanabe
  • Publication number: 20100112790
    Abstract: On a translucent substrate, an insulating film having a refractive index n and an amorphous silicon film are deposited successively. By irradiating the amorphous silicon film with a laser beam having a beam shape of a band shape extending along a length direction with a wavelength ?, a plurality of times from a side of amorphous silicon film facing the insulating film, while an irradiation position of the laser beam is shifted each of the plurality of times in a width direction of the band shape by a distance smaller than a width dimension of the band shape, a polycrystalline silicon film is formed from the amorphous silicon film. Forming the polycrystalline silicon film forms crystal grain boundaries which extend in the width direction and are disposed at a mean spacing measured along the length direction and ranging from (?/n)×0.95 to (?/n)×1.
    Type: Application
    Filed: December 5, 2007
    Publication date: May 6, 2010
    Applicant: Mitsubishi Electric Corproation
    Inventors: Kazuyuki Sugahara, Naoki Nakagawa, Shinsuke Yura, Toru Takeguchi, Tomoyuki Irizumi, Kazushi Yamayoshi, Atsuhiro Sono
  • Publication number: 20100078816
    Abstract: A display device includes a metal conductive layer formed on a substrate, a transparent electrode film formed on the substrate and joined to the metal conductive layer and an interlayer insulating film isolating the metal conductive layer and the transparent conductive film. The metal conductive layer has a lower aluminum layer made of aluminum or aluminum alloy, an intermediate impurity containing layer made of aluminum or aluminum alloy containing impurities and formed on a substantially entire upper surface of the lower aluminum layer and an upper aluminum layer made of aluminum or aluminum alloy and formed on the intermediate impurity containing layer. In the interlayer insulating film and the upper aluminum layer, a contact hole penetrates therethrough and locally exposes the intermediate impurity containing layer, and the transparent electrode film is joined to the metal conductive layer in the intermediate impurity containing layer exposed from the contact hole.
    Type: Application
    Filed: February 4, 2008
    Publication date: April 1, 2010
    Applicant: Mitsubishi Electric Corporation
    Inventors: Takumi Nakahata, Kazunori Inoue, Koji Oda, Naoki Nakagawa, Nobuaki Ishiga
  • Publication number: 20100060602
    Abstract: Each detection column wiring is constituted by a set of a first metal wiring having a zigzag pattern and a second metal wiring having a structure axisymmetric with the first metal wiring about a column direction as an axis, wherein the first metal wiring is constituted by first sloped portions which are obliquely sloped by an inclination angle of 45 degrees with respect to the column direction, and first parallel portions which are parallel with the column direction and are continuous with the first sloped portions, such that the first sloped portions and the first parallel portions are repeatedly placed in a zigzag shape along the column direction. Each detection row wiring also has the same structure. A sloped portion out of the first sloped portions of the first metal wiring is always orthogonally and spatially intersected, at its middle point, with a sloped portion out of the second sloped portions of the third metal wiring at its middle point.
    Type: Application
    Filed: September 3, 2009
    Publication date: March 11, 2010
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Masafumi AGARI, Takeshi ONO, Naoki NAKAGAWA, Isao NOJIRI, Hiroyuki MURAI, Takahiro NISHIOKA
  • Publication number: 20100053759
    Abstract: An antireflection coating is formed on a transparent substrate and includes an Al film having a transmittance of lower than 10% at a wavelength of 550 nm with a thickness of 25 nm and predominantly composed of aluminum (Al), and an Al—N film formed in at least one of an upper layer and a lower layer of the Al film, having a transmittance of equal to or higher than 10% at a wavelength of 550 nm with a thickness of 25 nm, predominantly composed of Al and at least containing a nitrogen (N) element as an additive. A specific resistance of the antireflection coating is equal to or lower than 1.0×10?2 O·cm, and a reflectance of a surface of the Al—N film is equal to or lower than 50% in a visible light region.
    Type: Application
    Filed: August 21, 2009
    Publication date: March 4, 2010
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kazunori INOUE, Naoki TSUMURA, Nobuaki ISHIGA, Takeshi ONO, Naoki NAKAGAWA, Masafumi AGARI, Yusuke YAMAGATA, Kensuke NAGAYAMA
  • Publication number: 20090290113
    Abstract: The display device includes a pair of insulating substrates arranged so as to be opposed, a bonding layer, and a strain suppressing plate. The bonding layer is provided on the outer surface side of one insulating substrate. The strain suppressing plate has rigidity higher than that of the insulating substrate to suppress the strain caused by curving the insulating substrate. The strain suppressing plate is fixed to the insulating substrate by the bonding layer.
    Type: Application
    Filed: May 26, 2009
    Publication date: November 26, 2009
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takumi Nakahata, Takanori Okumura, Yusuke Yamagata, Naoki Nakagawa, Masafumi Agari, Tetsuya Satake, Toru Kokogawa, Kenji Arita
  • Patent number: 7612378
    Abstract: A silicon nitride film and a silicon oxide film are formed on a glass substrate. On the silicon oxide film is formed a thin film transistor including a source region, a drain region, a channel region having a predetermined channel length, an LDD region and GOLD region having an impurity concentration higher than the impurity concentration of the channel region and lower than the impurity concentration of the source and drain regions, a gate insulation film, and a gate electrode. The gate electrode is formed to overlap in plane with the channel region and the GOLD region. Accordingly, a semiconductor device and an image display apparatus directed to improving source-drain breakdown voltage are obtained.
    Type: Grant
    Filed: March 16, 2006
    Date of Patent: November 3, 2009
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshihiko Toyoda, Naoki Nakagawa, Taro Yoshino
  • Patent number: 7553778
    Abstract: A method for producing a semiconductor device includes irradiating an amorphous semiconductor film on an insulating material with a pulsed laser beam having a rectangular irradiation area, while scanning in a direction intersecting a longitudinal direction of the irradiation area, thereby forming a first polycrystalline semiconductor film, and irradiating a part of the amorphous semiconductor film with the laser beam, while scanning in a longitudinal direction intersecting the irradiation area, the part superposing the first polycrystalline semiconductor film and being adjacent to the first polycrystalline semiconductor film, thereby forming a second polycrystalline semiconductor film. The laser beam has a wavelength in a range from 390 nm to 640 nm, and the amorphous semiconductor film has a thickness in a range from 60 nm to 100 nm.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: June 30, 2009
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazuyuki Sugahara, Naoki Nakagawa, Atsuhiro Sono, Shinsuke Yura, Kazushi Yamayoshi
  • Publication number: 20090159884
    Abstract: A method of manufacturing a thin-film transistor according to an embodiment of the present invention includes the step of forming a gate insulator on a gate electrode. The gate insulator includes at least a first region being in contact with a hydrogenated amorphous silicon film, and a second region positioned below the first region. The first and second regions are deposited using a source gas including NH3, N2, and SiH4, and H2 gas or a mixture of H2 and He. The first region is deposited by setting the flow-rate ratio NH3/SiH4 in a range from 11 to 14 and the second region is deposited by setting the flow-rate ratio NH3/SiH4 to be equal to or less than 4. It is thus possible to provide a thin-film transistor having excellent characteristics and high reliability, a method of manufacturing the same, and a display device including the thin-film transistor mounted thereon.
    Type: Application
    Filed: December 16, 2008
    Publication date: June 25, 2009
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Koji ODA, Naoki Nakagawa, Takeshi Ono, Yusuke Uchida
  • Publication number: 20090161048
    Abstract: In a liquid crystal display (10) having a curved display surface, long sides of pixel structures (11) are arranged along the curve direction (Y) of the display surface and on a side of counter substrate provided is a black matrix having a black matrix opening (41a) whose length in the curve direction (Y) is not longer than E?L {(T1/2)+(T2/2)+d}/R, assuming that the length of the display surface in the curve direction (Y) is L, the thickness of an array substrate is T1, the thickness of the counter substrate is T2, the size of the gap between the array substrate and the counter substrate is d, the radius of curvature of the curved display surface is R and the length of a long side of a pixel electrode (29) provided in each of the pixel structures (11) is E. It thereby becomes possible to suppress display unevenness resulting from positional misalignment of the two substrates due to curvature and provide a liquid crystal display achieving a high-quality display image.
    Type: Application
    Filed: December 8, 2008
    Publication date: June 25, 2009
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Tetsuya SATAKE, Takumi NAKAHATA, Takanori OKUMURA, Yusuke YAMAGATA, Takeshi ONO, Naoki NAKAGAWA, Suguru NAGAE
  • Patent number: 7541646
    Abstract: A thin film transistor device according to an embodiment of the invention includes: a thin film transistor having a silicon layer including a source region, a drain region, and a channel region, a gate insulating layer, and a gate electrode formed on an insulating substrate; an interlayer insulating layer covering the thin film transistor; a line electrically connected with the source region, the drain region, and the gate electrode through a contact hole formed in the interlayer insulating layer; a first upper insulating layer covering the line and the interlayer insulating layer and smoothing out stepped portions of the line and irregularities of a surface of the interlayer insulating layer; and a second upper insulating layer covering the first upper insulating layer, the second upper insulating layer having a hydrogen diffusion coefficient smaller than a hydrogen diffusion coefficient of the first upper insulating layer.
    Type: Grant
    Filed: February 12, 2007
    Date of Patent: June 2, 2009
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hitoshi Nagata, Takao Sakamoto, Naoki Nakagawa
  • Publication number: 20080224147
    Abstract: A thin film transistor includes a gate electrode, a gate insulating film formed to cover the gate electrode, a semiconductor layer including a channel region formed over the gate electrode, a source electrode and a drain electrode including a region connected to the semiconductor layer, where at least a part of the region is overlapped with the gate electrode, an upper insulating film formed to cover the semiconductor layer, the source electrode and the drain electrode, where the upper insulating film is directly in contact with the channel region of the semiconductor layer and discharges moisture by a heat treatment and a second upper insulating film formed to cover the first protective film and suppress moisture out-diffusion.
    Type: Application
    Filed: February 6, 2008
    Publication date: September 18, 2008
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hitoshi NAGATA, Naoki Nakagawa
  • Patent number: 7397521
    Abstract: A liquid crystal display according to the present invention includes: a liquid crystal cell 10, in which pixels having independently driven reflecting and transmitting members are arranged in a matrix, that is composed of a first substrate 15, a second substrate 17 having pixel driving members, and a liquid crystal 16 sandwiched between the first substrate 15 and the second substrate 17; a first polarizing means 13 disposed facing the first substrate 15; a second polarizing means 19 disposed facing the second substrate 17; a first front light 6 disposed outside the first polarizing means 13; and a second front light 7 disposed outside the second polarizing means 19. Owing to the configuration of the display, images can be displayed on both sides of the liquid crystal display.
    Type: Grant
    Filed: February 12, 2004
    Date of Patent: July 8, 2008
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Akimasa Yuuki, Naoki Nakagawa, Naoko Iwasaki, Shin Tahata, Keiichi Ito, Tomohiro Sasagawa, Takashi Yamamoto
  • Publication number: 20080017887
    Abstract: A thin film transistor array substrate according to an embodiment of the present invention includes: a semiconductor layer including a source region having a first conductivity type, a drain region having the first conductivity type, and a channel region between the source region and the drain region, and formed over a substrate; and a gate electrode opposite to the channel region with a gate insulating film interposed therebetween. The channel region contains an impurity of a second conductivity type doped with a predetermined distribution in a film thickness direction, and the impurity of the second conductivity type has a peak concentration point around an interface between the channel region and the insulating substrate or on the insulating substrate side.
    Type: Application
    Filed: July 16, 2007
    Publication date: January 24, 2008
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hitoshi NAGATA, Naoki NAKAGAWA, Takuji IMAMURA
  • Publication number: 20070241336
    Abstract: In first and second gate electrodes constituting a gate electrode, the gate length of the second gate electrode is set shorter than the gate length of the first gate electrode and short enough to produce the short channel effect. The threshold voltage of a second transistor corresponding to the second gate electrode can thereby be made lower than the threshold voltage of a first transistor corresponding to the first gate electrode. When the same voltage is applied to the first and second gate electrodes, an electric field concentration at the channel edge on the drain side is reduced. This in result reduces the channel length modulation effect.
    Type: Application
    Filed: April 12, 2007
    Publication date: October 18, 2007
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hidetada TOKIOKA, Naoki Nakagawa, Masafumi Agari
  • Publication number: 20070210353
    Abstract: A thin film transistor device according to an embodiment of the invention includes: a thin film transistor having a silicon layer including a source region, a drain region, and a channel region, a gate insulating layer, and a gate electrode formed on an insulating substrate; an interlayer insulating layer covering the thin film transistor; a line electrically connected with the source region, the drain region, and the gate electrode through a contact hole formed in the interlayer insulating layer; a first upper insulating layer covering the line and the interlayer insulating layer and smoothing out stepped portions of the line and irregularities of a surface of the interlayer insulating layer; and a second upper insulating layer covering the first upper insulating layer, the second upper insulating layer having a hydrogen diffusion coefficient smaller than a hydrogen diffusion coefficient of the first upper insulating layer.
    Type: Application
    Filed: February 12, 2007
    Publication date: September 13, 2007
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hitoshi NAGATA, Takao Sakamoto, Naoki Nakagawa
  • Patent number: D610679
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: February 23, 2010
    Assignee: Nipro Corporation
    Inventors: Naoki Nakagawa, Hidenori Takahashi, Toshikazu Hirayama