Abstract: A first thin film transistor including a gate electrode, a source region, a drain region, a GOLD region, and a channel region is formed at a first region at a TFT array substrate. A second thin film transistor including a gate electrode, a source region, drain region, a GOLD region, and a channel region is formed at a second region. The GOLD length (0.5 ?m) of the GOLD region of the second thin film transistor is set shorter than the GOLD length (1.5 ?m) of the GOLD region of the first thin film transistor. Accordingly, a semiconductor device directed to reducing the area occupied by semiconductor elements is obtained.

Abstract: A double-row self-aligning roller bearing includes left and right rows of rollers 4 and 5, arranged between an inner race 2 and an outer race 3. A raceway surface 3a of the outer race 3 represents a spherical shape and the rollers 4 and 5 have an outer peripheral surface following the shape of the raceway surface 3a of the outer race 3. The rollers 4 and 5 of the left and right roller rows have respective lengths L1 and L2 different from each other. Also, the left and right roller rows have respective contact angles ?1 and ?2 different from each other.

Abstract: A multi-pin connector for connecting a signal line on a backboard side and a signal line on a daughter board side has open pins where the signal lines are not connected. In order to prevent transmission loss on the signal lines caused by these open pins, terminating resistances are connected to both ends of the open pins, and ends of the terminating resistances opposite to the open pins are connected to ground or to a power supply.

Abstract: The present invention provides a display device capable of reducing cost by reduction in number of integrators. Signal lines (91 to 94, 95 to 98, 99 to 912, 913 to 916) are brought together into one line by means of signal lines (10a, 10b, 10c, 10d) to be connected to integrators (4a, 4b, 4c, 4d), respectively. Selector lines (71 to 74) orthogonal to the signal lines (91 to 916) are formed and connected to a selector driving circuit (3). An a-SiTFT (12) is formed at each of intersections: an intersection of the selector line (71) and the signal lines (91, 95, 99, 913); an intersection of the selector line (72) and the signal lines (92, 96, 910, 914); an intersection of the selector line (73) and the signal lines (93, 97, 911, 915); and an intersection of the selector line (74) and the signal lines (94, 98, 912, 916). The selector lines (71 to 74) are driven in sequence by the selector driving circuit (3) in the frame period.

Abstract: A silicon nitride film and a silicon oxide film are formed on a glass substrate. On the silicon oxide film is formed a thin film transistor including a source region, a drain region, a channel region having a predetermined channel length, an LDD region and GOLD region having an impurity concentration higher than the impurity concentration of the channel region and lower than the impurity concentration of the source and drain regions, a gate insulation film, and a gate electrode. The gate electrode is formed to overlap in plane with the channel region and the GOLD region. Accordingly, a semiconductor device and an image display apparatus directed to improving source-drain breakdown voltage are obtained.

Abstract: The widths of those portions of a semiconductor layer 5 and a drain line 6a overlapping with it which cross an edge line of a gate electrode 2 are made smaller than the channel width of a thin-film transistor. With this measure, the overlap area of the gate electrode 2 and a drain electrode 6 is reduced. As a result, a variation of the above overlap area due to alignment errors in a photolithography apparatus used in patterning the gate lines 2, the drain electrodes 6, and source electrodes 7 can be reduced and the frequency of occurrence of display defects can be decreased.

Abstract: A method for producing a semiconductor device includes irradiating an amorphous semiconductor film on an insulating material with a pulsed laser beam having a rectangular irradiation area, while scanning in a direction intersecting a longitudinal direction of the irradiation area, thereby forming a first polycrystalline semiconductor film, and irradiating a part of the amorphous semiconductor film with the laser beam, while scanning in a longitudinal direction intersecting the irradiation area, the part superposing the first polycrystalline semiconductor film and being adjacent to the first polycrystalline semiconductor film, thereby forming a second polycrystalline semiconductor film. The laser beam has a wavelength in a range from 390 nm to 640 nm, and the amorphous semiconductor film has a thickness in a range from 60 nm to 100 nm.

Abstract: A liquid crystal display according to the present invention includes: a liquid crystal cell 10, in which pixels having independently driven reflecting and transmitting members are arranged in a matrix, that is composed of a first substrate 15, a second substrate 17 having pixel driving members, and a liquid crystal 16 sandwiched between the first substrate 15 and the second substrate 17; a first polarizing means 13 disposed facing the first substrate 15; a second polarizing means 19 disposed facing the second substrate 17; a first front light 6 disposed outside the first polarizing means 13; and a second front light 7 disposed outside the second polarizing means 19. Owing to the configuration of the display, images can be displayed on both sides of the liquid crystal display.

Abstract: A first thin film transistor including a gate electrode, a source region, a drain region, a GOLD region, and a channel region is formed at a first region at a TFT array substrate. A second thin film transistor including a gate electrode, a source region, drain region, a GOLD region, and a channel region is formed at a second region. The GOLD length (0.5 ?m) of the GOLD region of the second thin film transistor is set shorter than the GOLD length (1.5 ?m) of the GOLD region of the first thin film transistor. Accordingly, a semiconductor device directed to reducing the area occupied by semiconductor elements is obtained.

Abstract: A silicon nitride film and a silicon oxide film are formed on a glass substrate. On the silicon oxide film is formed a thin film transistor including a source region, a drain region, a channel region having a predetermined channel length, a GOLD region and an LDD region having an impurity concentration lower than the impurity concentration of the source region, a GOLD region and an LDD region having an impurity concentration lower than the impurity concentration of the drain region, a gate insulation film, and a gate electrode. The gate electrode is formed overlapping with and facing the channel region and the GOLD region. A semiconductor device is obtained, directed to improving source-drain breakdown voltage and AC stress resistance, and achieving desired current property.

Abstract: A multi-pin connector for connecting a signal line on a backboard side and a signal line on a daughter board side has open pins where the signal lines are not connected. In order to prevent transmission loss on the signal lines caused by these open pins, terminating resistances are connected to both ends of the open pins, and ends of the terminating resistances opposite to the open pins are connected to ground or to a power supply.

Abstract: There is provided a cylindrical roller bearing (1) which includes an inner race (2), an outer race (3) and first, second and third rows of rollers (4A, 4B and 4C) accommodated within an annular bearing space delimited between the inner and outer races (2 and 3) with the second or intermediate row of the rollers (4B) positioned between the first and third rows of the rollers (4A and 4C). The rollers (4A and 4C) of the first and third rows have respective lengths (LA and LC) greater than the length (LB) of the rollers (4B) of the second row.

Abstract: The widths of those portions of a semiconductor layer 5 and a drain line 6a overlapping with it which cross an edge line of a gate electrode 2 are made smaller than the channel width of a thin-film transistor. With this measure, the overlap area of the gate electrode 2 and a drain electrode 6 is reduced. As a result, a variation of the above overlap area due to alignment errors in a photolithography apparatus used in patterning the gate lines 2, the drain electrodes 6, and source electrodes 7 can be reduced and the frequency of occurrence of display defects can be decreased.

Abstract: The widths of those portions of a semiconductor layer 5 and a drain line 6a overlapping with it which cross an edge line of a gate electrode 2 are made smaller than the channel width of a thin-film transistor. With this measure, the overlap area of the gate electrode 2 and a drain electrode 6 is reduced. As a result, a variation of the above overlap area due to alignment errors in a photolithography apparatus used in patterning the gate lines 2, the drain electrodes 6, and source electrodes 7 can be reduced and the frequency of occurrence of display defects can be decreased.

Abstract: The present invention is directed to a liquid crystal display device including: a thin film transistor (TFT) substrate having a plurality of displaying pixels each with a pixel electrode connected to respective TFT; a plurality of gate lines for scanning said TFTs in line-wise manner; a plurality of source lines for applying signal potential of writing picture to the pixels, arranged almost perpendicular with said gate lines in a matrix manner; an opposing substrate interposing a liquid crystal material together with the TFT array substrate therebetween; and a plurality of auxiliary capacitance electrode; wherein each of said pixel electrodes forms an auxiliary capacitance by overlapping with respective auxiliary capacitance electrode, said overlapping is decreased in a direction from a signal input side to a signal transmission end of each gate line to form a difference of auxiliary capacitance value depending on a plurality of vertical band regions, and boundaries of said vertical band regions are formed in

Abstract: An active matrix liquid crystal display of (2×1) dot inversion driving system, wherein in a case where the active matrix display is driven, voltage is applied to the pixels in such a manner that polarity is changed every source line in the horizontal direction and every two gate lines in the vertical direction. Further, a plurality of pixels is provided with a switching element, and charging characteristics of the pixels are made uniform both at the time of selecting the n-th line gate wire 1 at which the polarity of the source potential is inverted and at the time of selecting the (n+1)th line gate wire 2 at which no inversion is made in the source potential, whereby unevenness in luminance occurring in each line in raster display can be reduced.

Abstract: The object of the present invention is to provide a TFT array for obtaining a liquid crystal display apparatus of large screen size, of high aperture ratio, and of high precision without degrading the display quality through cross talks or shot blurs. The TFT array of the present invention is a TFT array substrate comprising: a transparent insulating substrate; a plurality of parallel gate electrode lines; a plurality of parallel source electrode lines crossing to the gate electrode lines; a plurality of TFTs located on each crossing point of the gate electrode lines and the source electrode lines; a passivation film formed on the TFTs; a plurality of transparent pixel electrodes formed on said passivation film corresponding to each said TFT and connected to a drain electrode of each said TFT via contact hole; a plurality of floating electrodes which serve as light shielding layer made of a same layer as that of said gate electrode lines formed in a peripheral portion of each said pixel electrode.

Abstract: Method for manufacturing a liquid crystal display apparatus including: a TFT array substrate having a plurality of scanning lines formed on a transparent insulating substrate by a metal film, a plurality of data lines formed on or beneath the scanning lines so as to be separated by an insulating film in such a manner as to intersect the scanning lines, switching elements that are formed by a semiconductor layer at respective intersections between the scanning lines and the data lines, and pixel electrodes that are formed by a transparent conductive film and electrically connected to the switching elements; and a counter substrate provided with a liquid crystal interposed between the TFT array substrate and the counter substrate; wherein a divisional exposing method is adopted as a patterning method on the TFT array substrate, so that adjacent exposing areas within a display area of the liquid crystal display apparatus have overlapped portions with each other, and so that a shot layout is defined in such a man

Abstract: The widths of those portions of a semiconductor layer 5 and a drain line 6a overlapping with it which cross an edge line of a gate electrode 2 are made smaller than the channel width of a thin-film transistor. With this measure, the overlap area of the gate electrode 2 and a drain electrode 6 is reduced. As a result, a variation of the above overlap area due to alignment errors in a photolithography apparatus used in patterning the gate lines 2, the drain electrodes 6, and source electrodes 7 can be reduced and the frequency of occurrence of display defects can be decreased.

Abstract: The liquid crystal display of the present invention comprising: a gate electrode line formed on an insulating substrate; a source electrode line including a source electrode intersected with said gate electrode line via an insulating film, a thin film transistor located in a vicinity of a portion in which said gate electrode line is intersected with said source electrode line; two drain electrode lines, each including two drain electrodes in said thin film transistor, said drain electrode line being connected with a pixel electrode; wherein said thin film transistor includes said two drain electrode lines located on both sides of said source electrode; said two drain electrodes being formed at a place where each end portion of said two drain electrode lines opposed to said source electrode is superposed with said gate electrode line.