Patents by Inventor Naoki Suzuki

Naoki Suzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110066259
    Abstract: A method of probing a projector performed on a projector system including a plurality of projectors and a control device adapted to control at least one of the projectors, the method includes the steps of: wherein the projectors, storing information indicative of time when the projector is powered on; and transmitting the information indicative of the time to the control device; and wherein the control device, probing the projectors to obtain the information indicative of the time when the projector is powered on; identifying the projector with the latest time when the projector powered on among the plurality of projectors based on the information indicative of the time, and displaying the identification information of the projector identified.
    Type: Application
    Filed: September 8, 2010
    Publication date: March 17, 2011
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Naoki SUZUKI
  • Publication number: 20110042691
    Abstract: This invention provides a means for suppressing streaks of light emission in an organic EL display having an organic light-emitting layer formed by coating by an ink jet method. A manufacturing process of the organic EL display of this invention includes: preparing a display substrate having two or more linear banks in parallel to each other, and two or more pixel regions arranged in a region between the linear banks; arranging an ink jet head such that the alignment direction of nozzles and the line direction of the linear banks are in parallel; and relatively moving the ink jet head in a direction perpendicular to the line direction of the linear banks and discharging the ink from the nozzles to apply the ink to every region defined by the linear banks.
    Type: Application
    Filed: May 25, 2009
    Publication date: February 24, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Hiroshi Hayata, Naoki Suzuki, Yoshio Kanata
  • Patent number: 7875974
    Abstract: To provide a stacked mounting structure in which the number of semiconductor chips that can be stacked is greater than conventionally, as well as a method for fabricating the same, each semiconductor chip has electrodes provided at least at one end in the stacked mounting structure, and a board holding the semiconductor chips at the one end is folded with at least two of the semiconductor chips being stacked so as to at least partially overlap with each other.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: January 25, 2011
    Assignee: Panasonic Corporation
    Inventors: Manabu Gokan, Akihisa Nakahashi, Naoki Suzuki, Haneo Iwamoto, Satoru Yuhaku
  • Publication number: 20100311298
    Abstract: It is an object to provide a functional-film fabricating method capable of forming uniform coating films without degrading the productivity, in the event of occurrence of non-ejectable nozzles, out of nozzles in an ink jet apparatus. A functional-film fabricating method includes the step of applying a coating by ejecting droplets of functional liquid (9) from plural nozzles (6) to ejection areas for forming a functional film which are surrounded by bounded areas (3) having a liquid repellent property, during a single scanning. In the step of applying the coating, when there is a non-ejectable nozzle out of plural nozzles to be used for applying a coating to a single ejection area, the amount of droplets of the functional liquid ejected form another ejectable nozzle to be used for applying a coating to this ejection area is made larger than that of cases where there is no non-ejectable nozzle.
    Type: Application
    Filed: June 7, 2010
    Publication date: December 9, 2010
    Inventors: Naoki SUZUKI, Takao Nagumo, Hidehiro Yoshida, Hiroshi Hayata, Masahiro Muro
  • Patent number: 7808094
    Abstract: A stacked structure of semiconductor chips includes plural stacked semiconductor chips and plural tabular holding members which hold the respective semiconductor chips.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: October 5, 2010
    Assignee: Panasonic Corporation
    Inventors: Manabu Gokan, Akihisa Nakahashi, Koichi Nagai, Naoki Suzuki
  • Patent number: 7771561
    Abstract: An apparatus and a method for surface treatment of substrates whereby the quality of substrates can be maintained by preventing excessive plasma treatment of substrates. In carrying out the plasma treatment on a surface of the substrate in a reaction chamber, there are provided an emission spectroscopic analysis device or a mass analyzer, and a controller, so that the energy of ions in plasma is controlled to decrease when, e.g., bromine included in the substrate is detected, and the surface treatment to the substrate is controlled to stop when the removal of impurities of the substrate is detected to end. The bromine once separated from the substrate is prevented from adhering again to the substrate and corroding the substrate. Moreover, ions are prevented from being excessively irradiated to the substrate when the removal of impurities ends, thereby reducing damage to the substrate.
    Type: Grant
    Filed: November 13, 2006
    Date of Patent: August 10, 2010
    Assignee: Panasonic Corporation
    Inventors: Naoki Suzuki, Kazuto Nishida, Kazuyuki Tomita
  • Publication number: 20100181937
    Abstract: An optical transmitter that can perform high-speed ON/OFF control of bias light that is input to an optical modulator. A high-speed current switching circuit performs a high-speed ON/OFF control of a drive current of an LD according to an LD ON/OFF signal. Thus, high-speed ON/OFF control of an optical output from the LD can be performed. A temperature detecting current generation circuit detects the ambient temperature, and generates the drive current adjusted according to the ambient temperature detected thereby so that the optical output from the LD is not affected by the ambient temperature.
    Type: Application
    Filed: July 13, 2007
    Publication date: July 22, 2010
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Masamichi Nogami, Masaki Noda, Naoki Suzuki
  • Publication number: 20100164575
    Abstract: Provided is a data recovery circuit including an input data phase detection circuit for outputting a gate signal synchronized with a rising phase of input data, a gated multiphase oscillator for instantly generating N-phase clocks based on the gate signal as a trigger, data discriminating and reproducing circuits for outputting sampled data of the input data which are synchronized with the clocks, a continuous clock generation circuit for generating a continuous clock which is a reference clock, continuous clock synchronization circuits for synchronizing the sampled data with the continuous clock and outputting the synchronized sampled data as phase synchronization data, and a phase selector for selecting the phase synchronization data having an optimum discrimination phase with the largest phase margin with respect to the input data and outputting the selected phase synchronization data as recovery data.
    Type: Application
    Filed: September 4, 2006
    Publication date: July 1, 2010
    Applicant: Mitsubishi Electric Corporation
    Inventors: Naoki Suzuki, Hitoyuki Tagami, Masamichi Nogami, Junichi Nakagawa
  • Publication number: 20100154989
    Abstract: A method for manufacturing a head-gimbal assembly. The head-gimbal assembly includes a head-slider bonded to a suspension. The method includes placing the head-slider and the suspension in a superposed manner with a photo-thermosetting adhesive applied between the head-slider and the suspension. The method also includes heating the suspension from a side of the suspension opposite to a side of the suspension in contact with the photo-thermosetting adhesive with a heated gas-stream. In addition, the method includes irradiating the photo-thermosetting adhesive with light at least partly in a time period during which the suspension is heated by the gas-stream.
    Type: Application
    Filed: December 18, 2009
    Publication date: June 24, 2010
    Inventors: Hideto IMAI, Tatsumi Tsuchiya, Eiki Oosawa, Naoki Suzuki
  • Publication number: 20100102581
    Abstract: A front shock absorbing structure of a vehicle includes a bumper reinforcement member that is disposed in a vehicle width direction in a front portion of a vehicle body and is formed as a rigid elongated member, and a shock absorbing member that is positioned on a front surface of the bumper reinforcement member. The shock absorbing member is vertically divided into a first shock absorbing portion and a second shock absorbing portion. The first and second shock absorbing portions are integrally coupled to each other at a forward side, so as to define a space therebetween at a rearward side. The coupling can be broken when an impact is applied by an impactor from ahead. The second shock absorbing portion has a protruding portion that is projected toward the space.
    Type: Application
    Filed: October 2, 2007
    Publication date: April 29, 2010
    Applicants: TOYOTA SHATAI KABUSHIKI KAISHA, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Naoki Goda, Naoki Suzuki
  • Patent number: 7638888
    Abstract: There is provided a semiconductor chip mounting substrate including a substrate on which a mounting region for mounting a semiconductor chip and a connection region for interlayer connection of the semiconductor chip are formed, and a plurality of alignment marks for alignment at the time of stacking which are provided around or in the connection region on the substrate, wherein a reinforcing member as a reinforcing region for reinforcing a portion between the plurality of alignment marks is provided on the substrate.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: December 29, 2009
    Assignee: Panasonic Corporation
    Inventors: Naoki Suzuki, Akihisa Nakahashi, Yukihiro Maegawa
  • Patent number: 7635016
    Abstract: In a board cleaning method for dry cleaning of connection sites on resin-based boards, one or more gases selected from a group consisting of gas that contains a hydrogen element and gas that contains a fluorine element are supplied at least to the connection sites, plasma is generated from the supplied gas, and the boards are cleaned by radicals and ions that are produced by the generated plasma.
    Type: Grant
    Filed: October 7, 2002
    Date of Patent: December 22, 2009
    Assignee: Panasonic Corporation
    Inventors: Naoki Suzuki, Youichi Nakamura, Kazuyuki Tomita
  • Patent number: 7592580
    Abstract: An input monitoring unit monitors full input light and outputs an input monitor signal. An output monitoring unit monitors full output light and outputs an output monitor signal. An ASE compensating circuit compensates for an ASE component contained in the output monitor signal. A gain-variation-level compensating circuit calculates a target average setup gain that is determined based on a signal intensity of the input monitor signal. A constant gain control circuit performs a gain control based on an output signal from the ASE compensating circuit and the target average setup gain.
    Type: Grant
    Filed: May 26, 2004
    Date of Patent: September 22, 2009
    Assignee: Mitsubishi Electric Corporation
    Inventors: Naoki Suzuki, Junichi Nakagawa
  • Publication number: 20090166838
    Abstract: To provide a stacked mounting structure in which the number of semiconductor chips that can be stacked is greater than conventionally, as well as a method for fabricating the same, each semiconductor chip has electrodes provided at least at one end in the stacked mounting structure, and a board holding the semiconductor chips at the one end is folded with at least two of the semiconductor chips being stacked so as to at least partially overlap with each other.
    Type: Application
    Filed: December 17, 2008
    Publication date: July 2, 2009
    Inventors: Manabu Gokan, Akihisa Nakahashi, Naoki Suzuki, Haneo Iwamoto, Satoru Yuhaku
  • Publication number: 20090166839
    Abstract: A semiconductor stack device having semiconductor chips stacked therein, wherein pads 4d of an uppermost semiconductor chip 2d are disposed on the side of a base substrate 1, and the pads 4d of the semiconductor chip 2d and electrodes 8d of the base substrate 1 are connected to each other via a flexible substrate 5 having circuit components 7 mounted thereon.
    Type: Application
    Filed: December 23, 2008
    Publication date: July 2, 2009
    Applicant: Panasonic Corporation
    Inventors: Naoki Suzuki, Akihisa Nakahashi, Haneo Iwamoto, Manabu Gokan, Satoru Yuhaku
  • Patent number: 7550715
    Abstract: A positive electrode drive unit enables a positive electrode to be repeatedly rotated about the center of the positive electrode to vary a distance between the positive electrode and an atom emission unit. A control unit receives input data which is set to obtain a desired atom density distribution by displacement of the positive electrode, and the control unit outputs a drive control signal for displacing the positive electrode to the positive electrode drive unit. The positive electrode drive unit is stopped during running by the control unit, or a drive speed of the positive electrode drive unit is changed by the control unit. Therefore, a residence time of each attitude is changed in the positive electrode to vary the atom density per unit time.
    Type: Grant
    Filed: April 26, 2007
    Date of Patent: June 23, 2009
    Assignee: Panasonic Corporation
    Inventors: Takashi Omura, Shinji Ishitani, Naoki Suzuki
  • Publication number: 20090098690
    Abstract: To realize high 2 performance and low power consumption of a semiconductor device by controlling electric characteristics of a transistor in accordance with a required function. Further, to manufacture such a semiconductor device with high yield and high productivity without complicating a manufacturing process. An impurity element imparting one conductivity type is added to a first semiconductor wafer in order to control the threshold voltage of a transistor included in the semiconductor device, before separating a single crystal semiconductor layer used as a channel formation region of the transistor from the first semiconductor wafer and transferring the single crystal semiconductor layer to a second semiconductor wafer.
    Type: Application
    Filed: October 8, 2008
    Publication date: April 16, 2009
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Takeshi SHICHI, Naoki SUZUKI
  • Publication number: 20090098674
    Abstract: To realize high performance and low power consumption of a semiconductor device by controlling electric characteristics of a transistor in accordance with a required function. Further, to manufacture such a semiconductor device with high yield and high productivity without complicating a manufacturing process. An impurity element imparting one conductivity type is added to a semiconductor substrate in order to control the threshold voltage of a transistor included in the semiconductor device, before separating a semiconductor layer of the transistor from the semiconductor substrate and transferring the semiconductor layer to a supporting substrate that is a substrate having an insulating surface.
    Type: Application
    Filed: October 7, 2008
    Publication date: April 16, 2009
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei YAMAZAKI, Takeshi SHICHI, Naoki SUZUKI
  • Patent number: 7442631
    Abstract: A doping method comprising the steps of; obtaining a proportion X of ions of a compound including a donor or an acceptor impurity in total ions from mass spectrum by using a first source gas of a first concentration; analyzing a peak concentration Y of the compound in a first processing object which is doped by using a second source gas of a second concentration equal to or lower than the first concentration, referring to a dose amount of total ions as D0 and setting an acceleration voltage at a value, obtaining a dose amount D1 of total ions from a expression, Y=(D1/D0)(aX+b), and doping a second processing object with the donor or the acceptor impurity by a ion doping apparatus using a third source gas, wherein a dose amount of total ions is set at D1, and an acceleration voltage is set at the value.
    Type: Grant
    Filed: February 3, 2006
    Date of Patent: October 28, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Naoki Suzuki
  • Publication number: 20080253242
    Abstract: A information recording medium includes a data area and a system area. In the data area, a user data is recorded. In the system area, management information for managing a recording status of the data area is recorded. The management information recorded in the system area includes recording mode information which indicates a recording procedure of the user data in the data area. By this construction, an information recording medium, a recording method of an information recording medium and an information recording and reproducing medium which are able to appropriately treat an information recording medium having an availability to a plurality of recording mode when being loaded.
    Type: Application
    Filed: August 14, 2007
    Publication date: October 16, 2008
    Applicant: NEC CORPORATION
    Inventors: Masatsugu Ogawa, Naoki Suzuki, Minoru Akiyama