Patents by Inventor Naoki Takeguchi

Naoki Takeguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11942429
    Abstract: A vertical repetition of multiple instances of a unit layer stack is formed over a substrate. The unit layer stack includes an insulating layer and a sacrificial material layer. Lateral recesses are formed by removing the sacrificial material layers selective to the insulating layers. Each lateral recess is sequentially fill with at least one conductive fill material and an insulating fill material, and vertically-extending portions of the at least one conductive fill material are removed such that a vertical layer stack including a first-type electrically conductive layer, a seamed insulating layer, and a second-type electrically conductive layer are formed in each lateral recess. Memory opening fill structures including a respective vertical stack of memory elements is formed through the insulating layers and the layer stacks. Memory openings, contact via cavities, or backside trenches may be used as access points for removing the sacrificial material layers.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: March 26, 2024
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Tatsuya Hinoue, Naoki Takeguchi, Masanori Tsutsumi, Seiji Shimabukuro
  • Publication number: 20230223248
    Abstract: A method of depositing a metal includes providing a structure a process chamber, and providing a metal fluoride gas and a growth-suppressant gas into the process chamber to deposit the metal over the structure. The metal may comprise a word line or another conductor of a three-dimensional memory device.
    Type: Application
    Filed: January 11, 2022
    Publication date: July 13, 2023
    Inventors: Fei ZHOU, Rahul SHARANGPANI, Raghuveer S. MAKALA, Yujin TERASAWA, Naoki TAKEGUCHI, Kensuke YAMAGUCHI, Masaaki HIGASHITANI
  • Publication number: 20230223266
    Abstract: A method of depositing a metal includes providing a structure a process chamber, and providing a metal fluoride gas and a growth-suppressant gas into the process chamber to deposit the metal over the structure. The metal may comprise a word line or another conductor of a three-dimensional memory device.
    Type: Application
    Filed: January 11, 2022
    Publication date: July 13, 2023
    Inventors: Fei ZHOU, Rahul SHARANGPANI, Raghuveer S. MAKALA, Yujin TERASAWA, Naoki TAKEGUCHI, Kensuke YAMAGUCHI, Masaaki HIGASHITANI
  • Publication number: 20230223267
    Abstract: A method of depositing a metal includes providing a structure a process chamber, and providing a metal fluoride gas and a growth-suppressant gas into the process chamber to deposit the metal over the structure. The metal may comprise a word line or another conductor of a three-dimensional memory device.
    Type: Application
    Filed: January 11, 2022
    Publication date: July 13, 2023
    Inventors: Rahul SHARANGPANI, Fei ZHOU, Raghuveer S. MAKALA, Yujin TERASAWA, Naoki TAKEGUCHI, Kensuke YAMAGUCHI
  • Publication number: 20230016319
    Abstract: A positive electrode for a lithium ion secondary battery includes a positive electrode current collector and a positive electrode mixture layer formed on one surface or both surfaces of the positive electrode current collector, wherein the positive electrode mixture layer contains a positive electrode active material, and conductive agent material, and a binder, the positive electrode active material is a mixture of a first positive electrode active material which is a lithium composite oxide with a layered structure and a second positive electrode material which is a polyanionic compound with an olivine type structure.
    Type: Application
    Filed: July 8, 2022
    Publication date: January 19, 2023
    Applicant: The Furukawa Battery Co., Ltd.
    Inventor: Naoki Takeguchi
  • Publication number: 20220406794
    Abstract: A three-dimensional memory device includes a vertical repetition of multiple instances of a unit layer stack, memory openings vertically extending through the vertical repetition, and memory opening fill structures located within the memory openings. Each of the memory opening fill structures contains a respective vertical stack of memory elements. The unit layer stack includes, from bottom to top or from top to bottom, a cavity-free insulating layer that is free of any cavity therein, a first-type electrically conductive layer, a cavity-containing insulating layer including an encapsulated cavity therein, and a second-type electrically conductive layer.
    Type: Application
    Filed: August 19, 2021
    Publication date: December 22, 2022
    Inventors: Tatsuya HINOUE, Naoki TAKEGUCHI
  • Publication number: 20220406720
    Abstract: A vertical repetition of multiple instances of a unit layer stack is formed over a substrate. The unit layer stack includes an insulating layer and a sacrificial material layer. Lateral recesses are formed by removing the sacrificial material layers selective to the insulating layers. Each lateral recess is sequentially fill with at least one conductive fill material and an insulating fill material, and vertically-extending portions of the at least one conductive fill material are removed such that a vertical layer stack including a first-type electrically conductive layer, a seamed insulating layer, and a second-type electrically conductive layer are formed in each lateral recess. Memory opening fill structures including a respective vertical stack of memory elements is formed through the insulating layers and the layer stacks. Access points for providing an etchant for removing the sacrificial material layers may be provided by memory openings, contact via cavities or backside trenches.
    Type: Application
    Filed: June 18, 2021
    Publication date: December 22, 2022
    Inventors: Tatsuya HINOUE, Naoki TAKEGUCHI, Masanori TSUTSUMI, Seiji SHIMABUKURO
  • Publication number: 20220406379
    Abstract: A vertical repetition of multiple instances of a unit layer stack is formed over a substrate. The unit layer stack includes an insulating layer and a sacrificial material layer. Lateral recesses are formed by removing the sacrificial material layers selective to the insulating layers. Each lateral recess is sequentially fill with at least one conductive fill material and an insulating fill material, and vertically-extending portions of the at least one conductive fill material are removed such that a vertical layer stack including a first-type electrically conductive layer, a seamed insulating layer, and a second-type electrically conductive layer are formed in each lateral recess. Memory opening fill structures including a respective vertical stack of memory elements is formed through the insulating layers and the layer stacks. Access points for providing an etchant for removing the sacrificial material layers may be provided by memory openings, contact via cavities or backside trenches.
    Type: Application
    Filed: June 18, 2021
    Publication date: December 22, 2022
    Inventors: Naoki TAKEGUCHI, Masanori TSUTSUMI, Seiji SHIMABUKURO, Tatsuya HINOUE
  • Publication number: 20220406793
    Abstract: A vertical repetition of multiple instances of a unit layer stack is formed over a substrate. The unit layer stack includes an insulating layer and a sacrificial material layer. Lateral recesses are formed by removing the sacrificial material layers selective to the insulating layers. Each lateral recess is sequentially fill with at least one conductive fill material and an insulating fill material, and vertically-extending portions of the at least one conductive fill material are removed such that a vertical layer stack including a first-type electrically conductive layer, a seamed insulating layer, and a second-type electrically conductive layer are formed in each lateral recess. Memory opening fill structures including a respective vertical stack of memory elements is formed through the insulating layers and the layer stacks. Access points for providing an etchant for removing the sacrificial material layers may be provided by memory openings, contact via cavities or backside trenches.
    Type: Application
    Filed: June 18, 2021
    Publication date: December 22, 2022
    Inventors: Naoki TAKEGUCHI, Masanori TSUTSUMI, Seiji SHIMABUKURO, Tatsuya HINOUE
  • Publication number: 20220352200
    Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening extending through the alternating stack, forming a sacrificial memory opening fill structure in the memory opening, replacing the sacrificial material layers with electrically conductive layers, removing the sacrificial memory opening fill structure selective to the electrically conductive layers, and forming a memory opening fill structure the memory opening after replacing the sacrificial material layers with electrically conductive layers and after removing the sacrificial memory opening fill structure. The memory opening fill structure includes a memory film and a vertical semiconductor channel.
    Type: Application
    Filed: November 10, 2021
    Publication date: November 3, 2022
    Inventors: Michiaki SANO, Yusuke MUKAE, Naoki TAKEGUCHI, Yujin TERASAWA, Tatsuya HINOUE, Ramy Nashed Bassely SAID
  • Publication number: 20220352199
    Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening extending through the alternating stack, forming a sacrificial memory opening fill structure in the memory opening, replacing the sacrificial material layers with electrically conductive layers, removing the sacrificial memory opening fill structure selective to the electrically conductive layers, and forming a memory opening fill structure the memory opening after replacing the sacrificial material layers with electrically conductive layers and after removing the sacrificial memory opening fill structure. The memory opening fill structure includes a memory film and a vertical semiconductor channel.
    Type: Application
    Filed: November 10, 2021
    Publication date: November 3, 2022
    Inventors: Yusuke MUKAE, Naoki TAKEGUCHI, Yujin TERASAWA, Tatsuya HINOUE, Ramy Nashed Bassely SAID
  • Patent number: 11377733
    Abstract: A method of depositing tungsten over a substrate includes disposing the substrate into a vacuum enclosure of a tungsten deposition apparatus, performing a first tungsten deposition process that deposits a first tungsten layer over a physically exposed surface of the substrate by flowing a fluorine-containing tungsten precursor gas into the vacuum enclosure, performing an in-situ oxidation process by exposing the first tungsten layer to an oxidation agent gas while the substrate remains within the vacuum enclosure without breaking vacuum and forming a tungsten oxyfluoride gas which is pumped out of the vacuum enclosure, and performing a second tungsten deposition process that deposits a second tungsten layer on the first tungsten layer by flowing the fluorine-containing tungsten precursor gas into the vacuum enclosure in a second tungsten deposition process after the in-situ oxidation process.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: July 5, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Fei Zhou, Raghuveer S. Makala, Rahul Sharangpani, Yusuke Mukae, Naoki Takeguchi
  • Publication number: 20220042171
    Abstract: A method of depositing tungsten over a substrate includes disposing the substrate into a vacuum enclosure of a tungsten deposition apparatus, performing a first tungsten deposition process that deposits a first tungsten layer over a physically exposed surface of the substrate by flowing a fluorine-containing tungsten precursor gas into the vacuum enclosure, performing an in-situ oxidation process by exposing the first tungsten layer to an oxidation agent gas while the substrate remains within the vacuum enclosure without breaking vacuum and forming a tungsten oxyfluoride gas which is pumped out of the vacuum enclosure, and performing a second tungsten deposition process that deposits a second tungsten layer on the first tungsten layer by flowing the fluorine-containing tungsten precursor gas into the vacuum enclosure in a second tungsten deposition process after the in-situ oxidation process.
    Type: Application
    Filed: August 7, 2020
    Publication date: February 10, 2022
    Inventors: Fei ZHOU, Raghuveer S. MAKALA, Rahul SHARANGPANI, Yusuke MUKAE, Naoki TAKEGUCHI
  • Patent number: 10916504
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Each of the memory stack structures includes a memory film and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers and the memory stack structures. Electrically conductive layers are formed in the backside recesses. Each of the electrically conductive layers includes a molybdenum-containing conductive liner and a metal fill portion including a metal other than molybdenum.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: February 9, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yusuke Mukae, Naoki Takeguchi, Kensuke Yamaguchi, Raghuveer S. Makala, Yujin Terasawa
  • Publication number: 20200395310
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Each of the memory stack structures includes a memory film and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers and the memory stack structures. Electrically conductive layers are formed in the backside recesses. Each of the electrically conductive layers includes a molybdenum-containing conductive liner and a metal fill portion including a metal other than molybdenum.
    Type: Application
    Filed: June 14, 2019
    Publication date: December 17, 2020
    Inventors: Yusuke MUKAE, Naoki TAKEGUCHI, Kensuke YAMAGUCHI, Raghuveer S. MAKALA, Yujin TERASAWA
  • Patent number: 10616984
    Abstract: A light-emitting diode (LED) lighting device includes (i) a selector circuit that sequentially and cyclically selects a plurality of LED loads one by one, the plurality of LED loads respectively emitting light as a result of being selected, and (ii) a control circuit that controls the selector circuit to cause an intermediate color to be produced by successively generating frames, each frame being a temporal combination of at least one first cycle period and at least one second cycle period, the at least one first cycle period generating a first mixed emission color, and the at least one second cycle period generating a second mixed emission color different from the first mixed emission color.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: April 7, 2020
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Naoki Takeguchi, Shigeru Ido, Hiroshi Kido
  • Patent number: 10608010
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed with stepped surfaces. Sacrificial metal plates are formed on the top surfaces of the sacrificial material layers, and a retro-stepped dielectric material portion is formed over the sacrificial metal plates. Contact via cavities are formed through the retro-stepped dielectric material portion employing the sacrificial metal plates as etch stop structures. The sacrificial metal plates are replaced with portions of insulating spacer layers. Sacrificial via fill structures within remaining volumes of the contact via cavities. The sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are replaced with portions of staircase-region contact via structures that contact the electrically conductive layers.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: March 31, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yujin Terasawa, Genta Mizuno, Yusuke Mukae, Yoshinobu Tanaka, Shiori Kataoka, Ryosuke Itou, Kensuke Yamaguchi, Naoki Takeguchi
  • Publication number: 20190364627
    Abstract: A light-emitting diode (LED) lighting device includes (i) a selector circuit that sequentially and cyclically selects a plurality of LED loads one by one, the plurality of LED loads respectively emitting light as a result of being selected, and (ii) a control circuit that controls the selector circuit to cause an intermediate color to be produced by successively generating frames, each frame being a temporal combination of at least one first cycle period and at least one second cycle period, the at least one first cycle period generating a first mixed emission color, and the at least one second cycle period generating a second mixed emission color different from the first mixed emission color.
    Type: Application
    Filed: April 30, 2019
    Publication date: November 28, 2019
    Inventors: Naoki TAKEGUCHI, Shigeru IDO, Hiroshi KIDO
  • Publication number: 20190280001
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed with stepped surfaces. Sacrificial metal plates are formed on the top surfaces of the sacrificial material layers, and a retro-stepped dielectric material portion is formed over the sacrificial metal plates. Contact via cavities are formed through the retro-stepped dielectric material portion employing the sacrificial metal plates as etch stop structures. The sacrificial metal plates are replaced with portions of insulating spacer layers. Sacrificial via fill structures within remaining volumes of the contact via cavities. The sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are replaced with portions of staircase-region contact via structures that contact the electrically conductive layers.
    Type: Application
    Filed: June 7, 2018
    Publication date: September 12, 2019
    Inventors: Yujin TERASAWA, Genta MIZUNO, Yusuke MUKAE, Yoshinobu TANAKA, Shiori KATAOKA, Ryosuke ITOU, Kensuke YAMAGUCHI, Naoki TAKEGUCHI
  • Patent number: 10381372
    Abstract: Void formation in tungsten lines in a three-dimensional memory device can be prevented by providing polycrystalline aluminum oxide liners in portions of lateral recesses that are laterally spaced from backside trenches by a distance grater than a predefined lateral offset distance. Tungsten nucleates on the polycrystalline aluminum oxide liners prior to nucleating on a metallic liner layer. Thus, tungsten layers can be deposited from the center portion of each backside recess, and the growth of tungsten can proceed toward the backside trenches. By forming the tungsten layers without voids, structural integrity of the three-dimensional memory device can be enhanced.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: August 13, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Fumitaka Amano, Takashi Arai, Genta Mizuno, Shigehisa Inoue, Naoki Takeguchi, Takashi Hamaya