Patents by Inventor Naoki Takeguchi

Naoki Takeguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10916504
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Each of the memory stack structures includes a memory film and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers and the memory stack structures. Electrically conductive layers are formed in the backside recesses. Each of the electrically conductive layers includes a molybdenum-containing conductive liner and a metal fill portion including a metal other than molybdenum.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: February 9, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yusuke Mukae, Naoki Takeguchi, Kensuke Yamaguchi, Raghuveer S. Makala, Yujin Terasawa
  • Publication number: 20200395310
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Each of the memory stack structures includes a memory film and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers and the memory stack structures. Electrically conductive layers are formed in the backside recesses. Each of the electrically conductive layers includes a molybdenum-containing conductive liner and a metal fill portion including a metal other than molybdenum.
    Type: Application
    Filed: June 14, 2019
    Publication date: December 17, 2020
    Inventors: Yusuke MUKAE, Naoki TAKEGUCHI, Kensuke YAMAGUCHI, Raghuveer S. MAKALA, Yujin TERASAWA
  • Patent number: 10616984
    Abstract: A light-emitting diode (LED) lighting device includes (i) a selector circuit that sequentially and cyclically selects a plurality of LED loads one by one, the plurality of LED loads respectively emitting light as a result of being selected, and (ii) a control circuit that controls the selector circuit to cause an intermediate color to be produced by successively generating frames, each frame being a temporal combination of at least one first cycle period and at least one second cycle period, the at least one first cycle period generating a first mixed emission color, and the at least one second cycle period generating a second mixed emission color different from the first mixed emission color.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: April 7, 2020
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Naoki Takeguchi, Shigeru Ido, Hiroshi Kido
  • Patent number: 10608010
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed with stepped surfaces. Sacrificial metal plates are formed on the top surfaces of the sacrificial material layers, and a retro-stepped dielectric material portion is formed over the sacrificial metal plates. Contact via cavities are formed through the retro-stepped dielectric material portion employing the sacrificial metal plates as etch stop structures. The sacrificial metal plates are replaced with portions of insulating spacer layers. Sacrificial via fill structures within remaining volumes of the contact via cavities. The sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are replaced with portions of staircase-region contact via structures that contact the electrically conductive layers.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: March 31, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yujin Terasawa, Genta Mizuno, Yusuke Mukae, Yoshinobu Tanaka, Shiori Kataoka, Ryosuke Itou, Kensuke Yamaguchi, Naoki Takeguchi
  • Publication number: 20190364627
    Abstract: A light-emitting diode (LED) lighting device includes (i) a selector circuit that sequentially and cyclically selects a plurality of LED loads one by one, the plurality of LED loads respectively emitting light as a result of being selected, and (ii) a control circuit that controls the selector circuit to cause an intermediate color to be produced by successively generating frames, each frame being a temporal combination of at least one first cycle period and at least one second cycle period, the at least one first cycle period generating a first mixed emission color, and the at least one second cycle period generating a second mixed emission color different from the first mixed emission color.
    Type: Application
    Filed: April 30, 2019
    Publication date: November 28, 2019
    Inventors: Naoki TAKEGUCHI, Shigeru IDO, Hiroshi KIDO
  • Publication number: 20190280001
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed with stepped surfaces. Sacrificial metal plates are formed on the top surfaces of the sacrificial material layers, and a retro-stepped dielectric material portion is formed over the sacrificial metal plates. Contact via cavities are formed through the retro-stepped dielectric material portion employing the sacrificial metal plates as etch stop structures. The sacrificial metal plates are replaced with portions of insulating spacer layers. Sacrificial via fill structures within remaining volumes of the contact via cavities. The sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are replaced with portions of staircase-region contact via structures that contact the electrically conductive layers.
    Type: Application
    Filed: June 7, 2018
    Publication date: September 12, 2019
    Inventors: Yujin TERASAWA, Genta MIZUNO, Yusuke MUKAE, Yoshinobu TANAKA, Shiori KATAOKA, Ryosuke ITOU, Kensuke YAMAGUCHI, Naoki TAKEGUCHI
  • Patent number: 10381372
    Abstract: Void formation in tungsten lines in a three-dimensional memory device can be prevented by providing polycrystalline aluminum oxide liners in portions of lateral recesses that are laterally spaced from backside trenches by a distance grater than a predefined lateral offset distance. Tungsten nucleates on the polycrystalline aluminum oxide liners prior to nucleating on a metallic liner layer. Thus, tungsten layers can be deposited from the center portion of each backside recess, and the growth of tungsten can proceed toward the backside trenches. By forming the tungsten layers without voids, structural integrity of the three-dimensional memory device can be enhanced.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: August 13, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Fumitaka Amano, Takashi Arai, Genta Mizuno, Shigehisa Inoue, Naoki Takeguchi, Takashi Hamaya
  • Patent number: 10128261
    Abstract: A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a metallic barrier material portion can be formed in each backside recess. A cobalt portion can be formed in each backside recess. Each backside recess can be filled with a cobalt portion alone, or can be filled with a combination of a cobalt portion and a metallic material portion including a material other than cobalt.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: November 13, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Raghuveer S. Makala, Rahul Sharangpani, Sateesh Koka, Genta Mizuno, Naoki Takeguchi, Senaka Krishna Kanakamedala, George Matamis, Yao-Sheng Lee, Johann Alsmeier
  • Patent number: 9887240
    Abstract: A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the immediately adjacent and isolated-from-one-another local bit lines to memory cells connected to the second of the pair of immediately adjacent and isolated-from-one-another local bit lines. A method programming a desire one of the memory cells includes applying boosting voltages to word lines adjacent to the bit line of the desired memory cell while not applying boosting voltages to word lines adjacent to the other bit line of the pair.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: February 6, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Seiji Shimabukuro, Teruyuki Mine, Hiroyuki Ogawa, Naoki Takeguchi
  • Publication number: 20180019256
    Abstract: Void formation in tungsten lines in a three-dimensional memory device can be prevented by providing polycrystalline aluminum oxide liners in portions of lateral recesses that are laterally spaced from backside trenches by a distance grater than a predefined lateral offset distance. Tungsten nucleates on the polycrystalline aluminum oxide liners prior to nucleating on a metallic liner layer. Thus, tungsten layers can be deposited from the center portion of each backside recess, and the growth of tungsten can proceed toward the backside trenches. By forming the tungsten layers without voids, structural integrity of the three-dimensional memory device can be enhanced.
    Type: Application
    Filed: October 24, 2016
    Publication date: January 18, 2018
    Inventors: Fumitaka AMANO, Takashi ARAI, Genta MIZUNO, Shigehisa INOUE, Naoki TAKEGUCHI, Takashi HAMAYA
  • Patent number: 9818798
    Abstract: Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and method of fabricating are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. Each gate is formed over the gate dielectric and a base that extends horizontally at least partially between adjacent pillars. The base is formed with notches filled with the gate dielectric. The select device is fabricated using a conformally deposited base dielectric material and conformal hard mask layer that is formed with a larger bottom thickness than horizontal thickness. The base thickness is defined by the deposition thickness, rather than an uncontrolled etch back.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: November 14, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Naoki Takeguchi, Hiroaki Iuchi
  • Publication number: 20170287925
    Abstract: A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a metallic barrier material portion can be formed in each backside recess. A cobalt portion can be formed in each backside recess. Each backside recess can be filled with a cobalt portion alone, or can be filled with a combination of a cobalt portion and a metallic material portion including a material other than cobalt.
    Type: Application
    Filed: February 4, 2015
    Publication date: October 5, 2017
    Inventors: Raghuveer S. MAKALA, Rahul SHARANGPANI, Sateesh KOKA, Genta MIZUNO, Naoki TAKEGUCHI, Senaka Krishna KANAKAMEDALA, George MATAMIS, Yao-Sheng LEE, Johann ALSMEIER
  • Publication number: 20170247794
    Abstract: A process chamber includes multiple partitions within a single continuous vacuum enclosure. Each of the multiple partitions is defined by respective distinct volumes within the single continuous vacuum enclosure that are connected thereamongst for unhindered movement of a substrate therethrough. The multiple partitions are configured to provide different process gases or purge gases to the substrate as the substrate cycles through the multiple positions. The process can cycle through a first deposition step that deposits a first material on the substrate in a first position and a second deposition step that deposits a second material on the substrate in a second position within each cycle. Alternatively or additionally, the process spaces can include at least one precursor treatment space and at least one reaction space.
    Type: Application
    Filed: July 26, 2016
    Publication date: August 31, 2017
    Inventors: Yusuke MUKAE, Fumitaka AMANO, Naoki TAKEGUCHI
  • Patent number: 9728499
    Abstract: A trench can be formed through a stack of alternating plurality of first material layers and second material layers. A dielectric material liner and a trench fill material portion can be formed in the trench. The dielectric material liner and portions of first material layer can be simultaneously etched to form laterally-extending cavities having level-dependent lateral extents. A set of stepped surfaces can be formed by removing unmasked portions of the second material layers. Alternately, an alternating sequence of processing steps including vertical etch processes and lateral recess processes can be employed to laterally recess second material layers and to form laterally-extending cavities having level-dependent lateral extents. Lateral cavities can be simultaneously formed in multiple levels such that levels having laterally-extending cavities of a same lateral extent are offset across multiple integrated cavities.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: August 8, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Seiji Shimabukuro, Hiroaki Iuchi, Michiaki Sano, Naoki Takeguchi
  • Publication number: 20170154925
    Abstract: A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the immediately adjacent and isolated-from-one-another local bit lines to memory cells connected to the second of the pair of immediately adjacent and isolated-from-one-another local bit lines. A method programming a desire one of the memory cells includes applying boosting voltages to word lines adjacent to the bit line of the desired memory cell while not applying boosting voltages to word lines adjacent to the other bit line of the pair.
    Type: Application
    Filed: February 13, 2017
    Publication date: June 1, 2017
    Applicant: SanDisk Technologies LLC
    Inventors: Seiji Shimabukuro, Teruyuki Mine, Hiroyuki Ogawa, Naoki Takeguchi
  • Patent number: 9608043
    Abstract: A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the immediately adjacent and isolated-from-one-another local bit lines to memory cells connected to the second of the pair of immediately adjacent and isolated-from-one-another local bit lines. A method programming a desire one of the memory cells includes applying boosting voltages to word lines adjacent to the bit line of the desired memory cell while not applying boosting voltages to word lines adjacent to the other bit line of the pair.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: March 28, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Seiji Shimabukuro, Teruyuki Mine, Hiroyuki Ogawa, Naoki Takeguchi
  • Patent number: 9601508
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. After formation of a memory opening, all surfaces of the memory opening are provided as silicon oxide surfaces by formation of at least one silicon oxide portion. A silicon nitride layer is formed in the memory opening. After formation of a memory stack structure, backside recesses can be formed employing the silicon oxide portions as an etch stop. The silicon oxide portions can be subsequently removed employing the silicon nitride layer as an etch stop. Physically exposed portions of the silicon nitride layer can be removed selective to the memory stack structure. Damage to the outer layer of the memory stack structure can be minimized or eliminated by successive use of etch stop structures. Electrically conductive layers can be subsequently formed in the backside recesses.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: March 21, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jongsun Sel, Chan Park, Atsushi Suyama, Frank Yu, Hiroyuki Ogawa, Ryoichi Honma, Kensuke Yamaguchi, Hiroaki Iuchi, Naoki Takeguchi, Tuan Pham, Kiyohiko Sakakibara, Jiao Chen
  • Publication number: 20160315095
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. After formation of a memory opening, all surfaces of the memory opening are provided as silicon oxide surfaces by formation of at least one silicon oxide portion. A silicon nitride layer is formed in the memory opening. After formation of a memory stack structure, backside recesses can be formed employing the silicon oxide portions as an etch stop. The silicon oxide portions can be subsequently removed employing the silicon nitride layer as an etch stop. Physically exposed portions of the silicon nitride layer can be removed selective to the memory stack structure. Damage to the outer layer of the memory stack structure can be minimized or eliminated by successive use of etch stop structures. Electrically conductive layers can be subsequently formed in the backside recesses.
    Type: Application
    Filed: October 23, 2015
    Publication date: October 27, 2016
    Inventors: Jongsun Sel, Chan Park, Atsushi Suyama, Frank Yu, Hiroyuki Ogawa, Ryoichi Honma, Kensuke Yamaguchi, Hiroaki Iuchi, Naoki Takeguchi, Tuan Pham, Kiyohiko Sakakibara, Jiao Chen
  • Publication number: 20160284765
    Abstract: Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and method of fabricating are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. Each gate is formed over the gate dielectric and a base that extends horizontally at least partially between adjacent pillars. The base is formed with notches filled with the gate dielectric. The select device is fabricated using a conformally deposited base dielectric material and conformal hard mask layer that is formed with a larger bottom thickness than horizontal thickness. The base thickness is defined by the deposition thickness, rather than an uncontrolled etch back.
    Type: Application
    Filed: June 3, 2016
    Publication date: September 29, 2016
    Applicant: SanDisk Technologies LLC
    Inventors: Naoki Takeguchi, Hiroaki Iuchi
  • Publication number: 20160268340
    Abstract: A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the immediately adjacent and isolated-from-one-another local bit lines to memory cells connected to the second of the pair of immediately adjacent and isolated-from-one-another local bit lines. A method programming a desire one of the memory cells includes applying boosting voltages to word lines adjacent to the bit line of the desired memory cell while not applying boosting voltages to word lines adjacent to the other bit line of the pair.
    Type: Application
    Filed: May 23, 2016
    Publication date: September 15, 2016
    Applicant: SanDisk Technologies LLC
    Inventors: Seiji Shimabukuro, Teruyuki Mine, Hiroyuki Ogawa, Naoki Takeguchi