Patents by Inventor Naoki Takeguchi
Naoki Takeguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10128261Abstract: A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a metallic barrier material portion can be formed in each backside recess. A cobalt portion can be formed in each backside recess. Each backside recess can be filled with a cobalt portion alone, or can be filled with a combination of a cobalt portion and a metallic material portion including a material other than cobalt.Type: GrantFiled: February 4, 2015Date of Patent: November 13, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Raghuveer S. Makala, Rahul Sharangpani, Sateesh Koka, Genta Mizuno, Naoki Takeguchi, Senaka Krishna Kanakamedala, George Matamis, Yao-Sheng Lee, Johann Alsmeier
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Patent number: 9887240Abstract: A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the immediately adjacent and isolated-from-one-another local bit lines to memory cells connected to the second of the pair of immediately adjacent and isolated-from-one-another local bit lines. A method programming a desire one of the memory cells includes applying boosting voltages to word lines adjacent to the bit line of the desired memory cell while not applying boosting voltages to word lines adjacent to the other bit line of the pair.Type: GrantFiled: February 13, 2017Date of Patent: February 6, 2018Assignee: SanDisk Technologies LLCInventors: Seiji Shimabukuro, Teruyuki Mine, Hiroyuki Ogawa, Naoki Takeguchi
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Publication number: 20180019256Abstract: Void formation in tungsten lines in a three-dimensional memory device can be prevented by providing polycrystalline aluminum oxide liners in portions of lateral recesses that are laterally spaced from backside trenches by a distance grater than a predefined lateral offset distance. Tungsten nucleates on the polycrystalline aluminum oxide liners prior to nucleating on a metallic liner layer. Thus, tungsten layers can be deposited from the center portion of each backside recess, and the growth of tungsten can proceed toward the backside trenches. By forming the tungsten layers without voids, structural integrity of the three-dimensional memory device can be enhanced.Type: ApplicationFiled: October 24, 2016Publication date: January 18, 2018Inventors: Fumitaka AMANO, Takashi ARAI, Genta MIZUNO, Shigehisa INOUE, Naoki TAKEGUCHI, Takashi HAMAYA
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Patent number: 9818798Abstract: Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and method of fabricating are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. Each gate is formed over the gate dielectric and a base that extends horizontally at least partially between adjacent pillars. The base is formed with notches filled with the gate dielectric. The select device is fabricated using a conformally deposited base dielectric material and conformal hard mask layer that is formed with a larger bottom thickness than horizontal thickness. The base thickness is defined by the deposition thickness, rather than an uncontrolled etch back.Type: GrantFiled: June 3, 2016Date of Patent: November 14, 2017Assignee: SanDisk Technologies LLCInventors: Naoki Takeguchi, Hiroaki Iuchi
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Publication number: 20170287925Abstract: A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a metallic barrier material portion can be formed in each backside recess. A cobalt portion can be formed in each backside recess. Each backside recess can be filled with a cobalt portion alone, or can be filled with a combination of a cobalt portion and a metallic material portion including a material other than cobalt.Type: ApplicationFiled: February 4, 2015Publication date: October 5, 2017Inventors: Raghuveer S. MAKALA, Rahul SHARANGPANI, Sateesh KOKA, Genta MIZUNO, Naoki TAKEGUCHI, Senaka Krishna KANAKAMEDALA, George MATAMIS, Yao-Sheng LEE, Johann ALSMEIER
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Publication number: 20170247794Abstract: A process chamber includes multiple partitions within a single continuous vacuum enclosure. Each of the multiple partitions is defined by respective distinct volumes within the single continuous vacuum enclosure that are connected thereamongst for unhindered movement of a substrate therethrough. The multiple partitions are configured to provide different process gases or purge gases to the substrate as the substrate cycles through the multiple positions. The process can cycle through a first deposition step that deposits a first material on the substrate in a first position and a second deposition step that deposits a second material on the substrate in a second position within each cycle. Alternatively or additionally, the process spaces can include at least one precursor treatment space and at least one reaction space.Type: ApplicationFiled: July 26, 2016Publication date: August 31, 2017Inventors: Yusuke MUKAE, Fumitaka AMANO, Naoki TAKEGUCHI
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Patent number: 9728499Abstract: A trench can be formed through a stack of alternating plurality of first material layers and second material layers. A dielectric material liner and a trench fill material portion can be formed in the trench. The dielectric material liner and portions of first material layer can be simultaneously etched to form laterally-extending cavities having level-dependent lateral extents. A set of stepped surfaces can be formed by removing unmasked portions of the second material layers. Alternately, an alternating sequence of processing steps including vertical etch processes and lateral recess processes can be employed to laterally recess second material layers and to form laterally-extending cavities having level-dependent lateral extents. Lateral cavities can be simultaneously formed in multiple levels such that levels having laterally-extending cavities of a same lateral extent are offset across multiple integrated cavities.Type: GrantFiled: November 26, 2014Date of Patent: August 8, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Seiji Shimabukuro, Hiroaki Iuchi, Michiaki Sano, Naoki Takeguchi
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Publication number: 20170154925Abstract: A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the immediately adjacent and isolated-from-one-another local bit lines to memory cells connected to the second of the pair of immediately adjacent and isolated-from-one-another local bit lines. A method programming a desire one of the memory cells includes applying boosting voltages to word lines adjacent to the bit line of the desired memory cell while not applying boosting voltages to word lines adjacent to the other bit line of the pair.Type: ApplicationFiled: February 13, 2017Publication date: June 1, 2017Applicant: SanDisk Technologies LLCInventors: Seiji Shimabukuro, Teruyuki Mine, Hiroyuki Ogawa, Naoki Takeguchi
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Patent number: 9608043Abstract: A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the immediately adjacent and isolated-from-one-another local bit lines to memory cells connected to the second of the pair of immediately adjacent and isolated-from-one-another local bit lines. A method programming a desire one of the memory cells includes applying boosting voltages to word lines adjacent to the bit line of the desired memory cell while not applying boosting voltages to word lines adjacent to the other bit line of the pair.Type: GrantFiled: May 23, 2016Date of Patent: March 28, 2017Assignee: SanDisk Technologies LLCInventors: Seiji Shimabukuro, Teruyuki Mine, Hiroyuki Ogawa, Naoki Takeguchi
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Patent number: 9601508Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. After formation of a memory opening, all surfaces of the memory opening are provided as silicon oxide surfaces by formation of at least one silicon oxide portion. A silicon nitride layer is formed in the memory opening. After formation of a memory stack structure, backside recesses can be formed employing the silicon oxide portions as an etch stop. The silicon oxide portions can be subsequently removed employing the silicon nitride layer as an etch stop. Physically exposed portions of the silicon nitride layer can be removed selective to the memory stack structure. Damage to the outer layer of the memory stack structure can be minimized or eliminated by successive use of etch stop structures. Electrically conductive layers can be subsequently formed in the backside recesses.Type: GrantFiled: October 23, 2015Date of Patent: March 21, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Jongsun Sel, Chan Park, Atsushi Suyama, Frank Yu, Hiroyuki Ogawa, Ryoichi Honma, Kensuke Yamaguchi, Hiroaki Iuchi, Naoki Takeguchi, Tuan Pham, Kiyohiko Sakakibara, Jiao Chen
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Publication number: 20160315095Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. After formation of a memory opening, all surfaces of the memory opening are provided as silicon oxide surfaces by formation of at least one silicon oxide portion. A silicon nitride layer is formed in the memory opening. After formation of a memory stack structure, backside recesses can be formed employing the silicon oxide portions as an etch stop. The silicon oxide portions can be subsequently removed employing the silicon nitride layer as an etch stop. Physically exposed portions of the silicon nitride layer can be removed selective to the memory stack structure. Damage to the outer layer of the memory stack structure can be minimized or eliminated by successive use of etch stop structures. Electrically conductive layers can be subsequently formed in the backside recesses.Type: ApplicationFiled: October 23, 2015Publication date: October 27, 2016Inventors: Jongsun Sel, Chan Park, Atsushi Suyama, Frank Yu, Hiroyuki Ogawa, Ryoichi Honma, Kensuke Yamaguchi, Hiroaki Iuchi, Naoki Takeguchi, Tuan Pham, Kiyohiko Sakakibara, Jiao Chen
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Publication number: 20160284765Abstract: Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and method of fabricating are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. Each gate is formed over the gate dielectric and a base that extends horizontally at least partially between adjacent pillars. The base is formed with notches filled with the gate dielectric. The select device is fabricated using a conformally deposited base dielectric material and conformal hard mask layer that is formed with a larger bottom thickness than horizontal thickness. The base thickness is defined by the deposition thickness, rather than an uncontrolled etch back.Type: ApplicationFiled: June 3, 2016Publication date: September 29, 2016Applicant: SanDisk Technologies LLCInventors: Naoki Takeguchi, Hiroaki Iuchi
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Publication number: 20160268340Abstract: A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the immediately adjacent and isolated-from-one-another local bit lines to memory cells connected to the second of the pair of immediately adjacent and isolated-from-one-another local bit lines. A method programming a desire one of the memory cells includes applying boosting voltages to word lines adjacent to the bit line of the desired memory cell while not applying boosting voltages to word lines adjacent to the other bit line of the pair.Type: ApplicationFiled: May 23, 2016Publication date: September 15, 2016Applicant: SanDisk Technologies LLCInventors: Seiji Shimabukuro, Teruyuki Mine, Hiroyuki Ogawa, Naoki Takeguchi
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Patent number: 9401279Abstract: A transistor gate is formed of a stack of layers including a polysilicon layer and a tungsten layer separated by a barrier layer. A titanium layer reduces interface resistance. A tungsten liner reduces sheet resistance. The tungsten liner, a tungsten nitride barrier layer, and the tungsten layer may be formed sequentially in the same chamber.Type: GrantFiled: June 14, 2013Date of Patent: July 26, 2016Assignee: SanDisk Technologies LLCInventor: Naoki Takeguchi
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Patent number: 9362338Abstract: Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and method of fabricating are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. Each gate is formed over the gate dielectric and a base that extends horizontally at least partially between adjacent pillars. The base is formed with notches filled with the gate dielectric. The select device is fabricated using a conformally deposited base dielectric material and conformal hard mask layer that is formed with a larger bottom thickness than horizontal thickness. The base thickness is defined by the deposition thickness, rather than an uncontrolled etch back.Type: GrantFiled: March 3, 2014Date of Patent: June 7, 2016Assignee: SanDisk Technologies Inc.Inventors: Naoki Takeguchi, Hiroaki Iuchi
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Patent number: 9356074Abstract: A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the immediately adjacent and isolated-from-one-another local bit lines to memory cells connected to the second of the pair of immediately adjacent and isolated-from-one-another local bit lines. A method programming a desire one of the memory cells includes applying boosting voltages to word lines adjacent to the bit line of the desired memory cell while not applying boosting voltages to word lines adjacent to the other bit line of the pair.Type: GrantFiled: November 17, 2014Date of Patent: May 31, 2016Assignee: SanDisk Technologies Inc.Inventors: Seiji Shimabukuro, Teruyuki Mine, Hiroyuki Ogawa, Naoki Takeguchi
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Publication number: 20160148835Abstract: A trench can be formed through a stack of alternating plurality of first material layers and second material layers. A dielectric material liner and a trench fill material portion can be formed in the trench. The dielectric material liner and portions of first material layer can be simultaneously etched to form laterally-extending cavities having level-dependent lateral extents. A set of stepped surfaces can be formed by removing unmasked portions of the second material layers. Alternately, an alternating sequence of processing steps including vertical etch processes and lateral recess processes can be employed to laterally recess second material layers and to form laterally-extending cavities having level-dependent lateral extents. Lateral cavities can be simultaneously formed in multiple levels such that levels having laterally-extending cavities of a same lateral extent are offset across multiple integrated cavities.Type: ApplicationFiled: November 26, 2014Publication date: May 26, 2016Inventors: Seiji SHIMABUKURO, Hiroaki IUCHI, Michiaki SANO, Naoki TAKEGUCHI
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Publication number: 20160141337Abstract: A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the immediately adjacent and isolated-from-one-another local bit lines to memory cells connected to the second of the pair of immediately adjacent and isolated-from-one-another local bit lines. A method programming a desire one of the memory cells includes applying boosting voltages to word lines adjacent to the bit line of the desired memory cell while not applying boosting voltages to word lines adjacent to the other bit line of the pair.Type: ApplicationFiled: November 17, 2014Publication date: May 19, 2016Applicant: SANDISK 3D LLCInventors: Sejei Shimabukuro, Teruyuki Mine, Hiroyuki Ogawa, Naoki Takeguchi
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Patent number: 9337085Abstract: Air gaps are formed between bit lines by etching to remove sacrificial material from between bit lines. Bit lines are protected from etch damage. Sacrificial material may be selectively oxidized prior to deposition of bit line metal so that protective oxide lies along sides of bit lines during etch. Portions of protective material may be selectively formed on tops of bit lines prior to etching sacrificial material.Type: GrantFiled: July 25, 2014Date of Patent: May 10, 2016Assignee: SanDisk Technologies Inc.Inventors: Jong Sun Sel, Marika Gunji-Yoneoka, Naoki Takeguchi, Chan Park, Tuan D. Pham, Kazuya Tokunaga
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Patent number: 9334578Abstract: An electroplating system is provided. The electroplating system includes a divided electrode that is arranged to simultaneously provide a plurality of line currents for an electroplating process. The system includes a current control component that is coupled to the divided electrode. The current control component is configured to determine the magnitude of each of the line currents. The current control component is also configured to regulate individual line currents based, at least in part, on the determined magnitude of each of the line currents.Type: GrantFiled: November 18, 2008Date of Patent: May 10, 2016Assignee: Cypress Semiconductor CorporationInventor: Naoki Takeguchi