Patents by Inventor Naoki Takeguchi

Naoki Takeguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9401279
    Abstract: A transistor gate is formed of a stack of layers including a polysilicon layer and a tungsten layer separated by a barrier layer. A titanium layer reduces interface resistance. A tungsten liner reduces sheet resistance. The tungsten liner, a tungsten nitride barrier layer, and the tungsten layer may be formed sequentially in the same chamber.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: July 26, 2016
    Assignee: SanDisk Technologies LLC
    Inventor: Naoki Takeguchi
  • Patent number: 9362338
    Abstract: Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and method of fabricating are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. Each gate is formed over the gate dielectric and a base that extends horizontally at least partially between adjacent pillars. The base is formed with notches filled with the gate dielectric. The select device is fabricated using a conformally deposited base dielectric material and conformal hard mask layer that is formed with a larger bottom thickness than horizontal thickness. The base thickness is defined by the deposition thickness, rather than an uncontrolled etch back.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: June 7, 2016
    Assignee: SanDisk Technologies Inc.
    Inventors: Naoki Takeguchi, Hiroaki Iuchi
  • Patent number: 9356074
    Abstract: A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the immediately adjacent and isolated-from-one-another local bit lines to memory cells connected to the second of the pair of immediately adjacent and isolated-from-one-another local bit lines. A method programming a desire one of the memory cells includes applying boosting voltages to word lines adjacent to the bit line of the desired memory cell while not applying boosting voltages to word lines adjacent to the other bit line of the pair.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: May 31, 2016
    Assignee: SanDisk Technologies Inc.
    Inventors: Seiji Shimabukuro, Teruyuki Mine, Hiroyuki Ogawa, Naoki Takeguchi
  • Publication number: 20160148835
    Abstract: A trench can be formed through a stack of alternating plurality of first material layers and second material layers. A dielectric material liner and a trench fill material portion can be formed in the trench. The dielectric material liner and portions of first material layer can be simultaneously etched to form laterally-extending cavities having level-dependent lateral extents. A set of stepped surfaces can be formed by removing unmasked portions of the second material layers. Alternately, an alternating sequence of processing steps including vertical etch processes and lateral recess processes can be employed to laterally recess second material layers and to form laterally-extending cavities having level-dependent lateral extents. Lateral cavities can be simultaneously formed in multiple levels such that levels having laterally-extending cavities of a same lateral extent are offset across multiple integrated cavities.
    Type: Application
    Filed: November 26, 2014
    Publication date: May 26, 2016
    Inventors: Seiji SHIMABUKURO, Hiroaki IUCHI, Michiaki SANO, Naoki TAKEGUCHI
  • Publication number: 20160141337
    Abstract: A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the immediately adjacent and isolated-from-one-another local bit lines to memory cells connected to the second of the pair of immediately adjacent and isolated-from-one-another local bit lines. A method programming a desire one of the memory cells includes applying boosting voltages to word lines adjacent to the bit line of the desired memory cell while not applying boosting voltages to word lines adjacent to the other bit line of the pair.
    Type: Application
    Filed: November 17, 2014
    Publication date: May 19, 2016
    Applicant: SANDISK 3D LLC
    Inventors: Sejei Shimabukuro, Teruyuki Mine, Hiroyuki Ogawa, Naoki Takeguchi
  • Patent number: 9337085
    Abstract: Air gaps are formed between bit lines by etching to remove sacrificial material from between bit lines. Bit lines are protected from etch damage. Sacrificial material may be selectively oxidized prior to deposition of bit line metal so that protective oxide lies along sides of bit lines during etch. Portions of protective material may be selectively formed on tops of bit lines prior to etching sacrificial material.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: May 10, 2016
    Assignee: SanDisk Technologies Inc.
    Inventors: Jong Sun Sel, Marika Gunji-Yoneoka, Naoki Takeguchi, Chan Park, Tuan D. Pham, Kazuya Tokunaga
  • Patent number: 9334578
    Abstract: An electroplating system is provided. The electroplating system includes a divided electrode that is arranged to simultaneously provide a plurality of line currents for an electroplating process. The system includes a current control component that is coupled to the divided electrode. The current control component is configured to determine the magnitude of each of the line currents. The current control component is also configured to regulate individual line currents based, at least in part, on the determined magnitude of each of the line currents.
    Type: Grant
    Filed: November 18, 2008
    Date of Patent: May 10, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventor: Naoki Takeguchi
  • Patent number: 9330969
    Abstract: Air gaps are formed between bit lines by etching to remove sacrificial material from between bit lines. Bit lines are protected from etch damage. Sacrificial material may be selectively oxidized prior to deposition of bit line metal so that protective oxide lies along sides of bit lines during etch. Portions of protective material may be selectively formed on tops of bit lines prior to etching sacrificial material.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: May 3, 2016
    Assignee: SanDisk Technologies Inc.
    Inventors: Jong Sun Sel, Marika Gunji-Yoneoka, Naoki Takeguchi, Chan Park, Tuan D. Pham, Kazuya Tokunaga
  • Patent number: 9281384
    Abstract: Structures and methods for blocking ultraviolet rays during a film depositing process for semiconductor device are disclosed. In one embodiment, a semiconductor device includes an oxide-nitride-oxide (ONO) film formed on a semiconductor substrate, a gate electrode formed on the ONO film, a lower layer insulation film formed on the ONO film and the gate electrode, and a ultraviolet (UV) blocking layer based on a plurality of granular particles scattered in at least one insulation film formed on lower layer insulation film, where the UV blocking layer suppresses UV rays generated during an additional film deposition from reaching the ONO film.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: March 8, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventor: Naoki Takeguchi
  • Patent number: 9230984
    Abstract: A monolithic three dimensional memory device includes a comb-shaped electrode within a trench, where the electrode includes an elongated continuous portion of an electrically conductive material that is raised from a major surface of a substrate and a plurality of second portions that include spaced-apart conductive pillars extending between the continuous portion and the major surface of the substrate. A fill material, such as a dielectric material, is located between the plurality of second portions.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: January 5, 2016
    Assignee: SANDISK TECHNOLOGIES INC
    Inventor: Naoki Takeguchi
  • Patent number: 9159739
    Abstract: A monolithic three dimensional NAND string includes a semiconductor channel, with at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, and a plurality of copper containing control gate electrodes extending substantially parallel to the major surface of the substrate. The plurality of control gate electrodes include at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level. The NAND string also includes a blocking dielectric located over the plurality of control gates, a tunnel dielectric in contact with the semiconductor channel, and at least one charge storage region located between the blocking dielectric and the tunnel dielectric.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: October 13, 2015
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Raghuveer S. Makala, Yanli Zhang, Yao-Sheng Lee, Senaka Krishna Kanakamedala, Rahul Sharangpani, George Matamis, Johann Alsmeier, Seiji Shimabukuro, Genta Mizuno, Naoki Takeguchi
  • Publication number: 20150249112
    Abstract: Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and method of fabricating such a memory are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. Each gate is formed over the gate dielectric and a base that extends horizontally at least partially between adjacent pillars. The base is formed with notches that are filled with the gate dielectric. The select device is fabricated using a conformally deposited base dielectric material and conformal hard mask layer that is formed with a larger bottom thickness than horizontal thickness. The hard mask permits the base thickness to be defined by the deposition thickness, rather than an uncontrolled etch back.
    Type: Application
    Filed: March 3, 2014
    Publication date: September 3, 2015
    Applicant: SanDisk 3D LLC
    Inventors: Naoki Takeguchi, Hiroaki Iuchi
  • Publication number: 20150228582
    Abstract: Air gaps are formed between bit lines by etching to remove sacrificial material from between bit lines. Bit lines are protected from etch damage. Sacrificial material may be selectively oxidized prior to deposition of bit line metal so that protective oxide lies along sides of bit lines during etch. Portions of protective material may be selectively formed on tops of bit lines prior to etching sacrificial material.
    Type: Application
    Filed: July 25, 2014
    Publication date: August 13, 2015
    Inventors: Jong Sun Sel, Marika Gunji-Yoneoka, Naoki Takeguchi, Chan Park, Tuan D. Pham, Kazuya Tokunaga
  • Publication number: 20150228532
    Abstract: Air gaps are formed between bit lines by etching to remove sacrificial material from between bit lines. Bit lines are protected from etch damage. Sacrificial material may be selectively oxidized prior to deposition of bit line metal so that protective oxide lies along sides of bit lines during etch. Portions of protective material may be selectively formed on tops of bit lines prior to etching sacrificial material.
    Type: Application
    Filed: July 25, 2014
    Publication date: August 13, 2015
    Inventors: Jong Sun Sel, Marika Gunji-Yoneoka, Naoki Takeguchi, Chan Park, Tuan D. Pham, Kazuya Tokunaga
  • Publication number: 20150179662
    Abstract: A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a metallic barrier material portion can be formed in each backside recess. A cobalt portion can be formed in each backside recess. Each backside recess can be filled with a cobalt portion alone, or can be filled with a combination of a cobalt portion and a metallic material portion including a material other than cobalt.
    Type: Application
    Filed: February 4, 2015
    Publication date: June 25, 2015
    Inventors: Raghuveer S. MAKALA, Rahul SHARANGPANI, Sateesh KOKA, Genta MIZUNO, Naoki TAKEGUCHI, Senaka Krishna KANAKAMEDALA, George MATAMIS, Yao-Sheng LEE, Johann ALSMEIER
  • Publication number: 20140367804
    Abstract: A transistor gate is formed of a stack of layers including a polysilicon layer and a tungsten layer separated by a barrier layer. A titanium layer reduces interface resistance. A tungsten liner reduces sheet resistance. The tungsten liner, a tungsten nitride barrier layer, and the tungsten layer may be formed sequentially in the same chamber.
    Type: Application
    Filed: June 14, 2013
    Publication date: December 18, 2014
    Inventor: Naoki Takeguchi
  • Publication number: 20140353738
    Abstract: A method of making a monolithic three dimensional NAND string including providing a stack of alternating first material layers and second material layers over a substrate. The first material layers comprise an insulating material and the second material layers comprise sacrificial layers. The method also includes forming a back side opening in the stack, selectively removing the second material layers through the back side opening to form back side recesses between adjacent first material layers and forming a blocking dielectric inside the back side recesses and the back side opening. The blocking dielectric has a clam shaped regions inside the back side recesses. The method also includes forming a plurality of copper control gate electrodes in the respective clam shell shaped regions of the blocking dielectric in the back side recesses.
    Type: Application
    Filed: August 20, 2014
    Publication date: December 4, 2014
    Inventors: Raghuveer S. Makala, Yanli Zhang, Yao-Sheng Lee, Senaka Krishna Kanakamedala, Rahul Sharangpani, George Matamis, Johann Alsmeier, Seiji Shimabukuro, Genta Mizuno, Naoki Takeguchi
  • Patent number: 8835248
    Abstract: Techniques for fabricating metal lines in semiconductor systems are disclosed. The metal may be tungsten. A hybrid Chemical Vapor Deposition (CVD)/Physical Vapor Deposition (PVD) process may be used. A layer of tungsten may be formed using CVD. This CVD layer may be formed over a barrier layer, such as, but not limited to, TiN or WN. This CVD layer may completely fill some feature such as a trench or via. Then, a layer of tungsten may be formed over the CVD layer using PVD. The layers of tungsten may then be etched to form a wire or line. Techniques for forming metal wires using a hybrid CVD/PVD process may provide for low resistivity with a barrier metal, low surface roughness, and good gap filling.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: September 16, 2014
    Assignee: SanDisk Technologies Inc.
    Inventor: Naoki Takeguchi
  • Patent number: 8749012
    Abstract: Methods and structures for discharging plasma formed during the fabrication of semiconductor device are disclosed. The semiconductor device includes a wordline, a common ground line and a fuse structure for electrically coupling the wordline and the common ground line until a break signal is applied via the fuse structure.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: June 10, 2014
    Assignee: Spansion LLC
    Inventors: Masahiko Higashi, Naoki Takeguchi
  • Publication number: 20130316531
    Abstract: Techniques for fabricating metal lines in semiconductor systems are disclosed. The metal may be tungsten. A hybrid Chemical Vapor Deposition (CVD)/Physical Vapor Deposition (PVD) process may be used. A layer of tungsten may be formed using CVD. This CVD layer may be formed over a barrier layer, such as, but not limited to, TiN or WN. This CVD layer may completely fill some feature such as a trench or via. Then, a layer of tungsten may be formed over the CVD layer using PVD. The layers of tungsten may then be etched to form a wire or line. Techniques for forming metal wires using a hybrid CVD/PVD process may provide for low resistivity with a barrier metal, low surface roughness, and good gap filling.
    Type: Application
    Filed: May 24, 2012
    Publication date: November 28, 2013
    Inventor: Naoki Takeguchi