Patents by Inventor Naoki Yasuda

Naoki Yasuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210221815
    Abstract: The present invention is directed to processes for preparing beta 3 agonists of Formula (I) and Formula (II) and their intermediates. The beta 3 agonists are useful in the treatment of certain disorders, including overactive bladder, urinary incontinence, and urinary urgency.
    Type: Application
    Filed: January 22, 2021
    Publication date: July 22, 2021
    Applicant: Merck Sharp & Dohme Corp.
    Inventors: John Y.L. CHUNG, Kevin CAMPOS, Edward CLEATOR, Robert F. DUNN, Andrew GIBSON, R. Scott HOERRNER, Stephen KEEN, Dave LIEBERMAN, Zhuqing LIU, Joseph LYNCH, Kevin M. MALONEY, Feng XU, Nobuyoshi YASUDA, Naoki YOSHIKAWA, Yong-Li ZHONG
  • Publication number: 20210183535
    Abstract: In the insulation sheet, an insulation resin layer made of a thermosetting resin composition in an uncured or semi-cured state is formed on one or each of both surfaces of the base material. The thermosetting resin composition contains: a thermosetting resin (A) that is in solid form at 25° C.; a thermosetting resin (B) that is in liquid form at 25° C.; a latent curing agent that is unreactive at 60° C. or lower; and an inorganic filler having a maximum particle diameter smaller than a film thickness of the insulation resin layer and having an average particle diameter smaller than 0.5 times the film thickness. The insulation resin layer of the insulation sheet is efficiently compressed into a predetermined thickness by pressure application at normal temperature and permeates a gap between a stator core and a stator coil by heating during curing treatment, whereby both members can be insulated and fixed.
    Type: Application
    Filed: October 28, 2020
    Publication date: June 17, 2021
    Applicant: Mitsubishi Electric Corporation
    Inventors: Shiori NATORI, Naoki YASUDA, Kazuya HASEGAWA, Kenji MAEKAWA, Yasuhiro HAYASAKA
  • Patent number: 11001729
    Abstract: A coating material of the present invention includes an insulating resin, and dispersion particles dispersed in the insulating resin. The dispersion particle includes a core particle containing zinc oxide as a main component and having nonlinear resistance, and a resin layer covering the surface of the core particle and having an average thickness being less than or equal to 5.0 ?m. The coating material of the present invention is a coating material for coating an inner surface of a ground tank of a gas insulated switchgear.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: May 11, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Satoru Sato, Naoki Yasuda, Nobuo Yokomura, Ryoko Kawano, Manabu Yoshimura, Shinichiro Nakauchi
  • Publication number: 20210130603
    Abstract: The thermosetting resin composition is used for a sheet-form insulating varnish to be disposed in a gap between insulation target members, and contains: a thermosetting resin (A) that is in solid form at 25° C.; a thermosetting resin (B) that is in liquid form at 25° C.; a latent curing agent that is unreactive at 60° C. or lower; and an inorganic filler having a maximum particle diameter smaller than a dimension of the gap and having an average particle diameter smaller than 0.5 times the dimension of the gap. 30 parts by mass to 70 parts by mass of the thermosetting resin (A) is contained per a total of 100 parts by mass of the thermosetting resin (A) and the thermosetting resin (B). A volume ratio of the inorganic filler to an entirety of the composition is not higher than 50%.
    Type: Application
    Filed: July 22, 2020
    Publication date: May 6, 2021
    Applicant: Mitsubishi Electric Corporation
    Inventors: Naoki YASUDA, Shiori NATORI, Kazuya HASEGAWA, Shogo OKAMOTO
  • Publication number: 20210114751
    Abstract: A power supply device (104-1) includes a substrate (20) on which an electric component (25) is mounted, a chassis (10) having a chassis surface (11) and a threaded part (10a), a chassis-side resin part (91) connected to a back surface (20a) and the chassis surface (11), a fixation screw (29), and an insulating member (60). The fixation screw (29) fixes both the electric component (25) and the substrate (20) to the chassis (10) by screw-coupling an end part (29c) of the fixation screw (29), exposed in a direction toward the chassis (10) from an open hole formed through the insulating member (60), to the threaded part (10a) of the chassis (10). In addition, the fixation screw (29) brings the electric component (25) and the chassis (10) into electrical noncontact with each other by being placed in an open hole of the insulating member (60).
    Type: Application
    Filed: June 27, 2018
    Publication date: April 22, 2021
    Applicant: Mitsubishi Electric Corporation
    Inventors: Takashi MIYAMOTO, Naoki YASUDA, Shinichi OKADA, Ryota KUSANO
  • Publication number: 20200161316
    Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode members and a plurality of insulating members, each of the electrode members and each of the insulating members being stacked alternately in a first direction on the substrate. The semiconductor memory device also includes a memory hole that extends in the stacked body in the first direction and a semiconductor member that is disposed to extend in the memory hole in the first direction. The semiconductor memory device also includes a memory member that is disposed between the semiconductor member and the plurality of electrode members. The plurality of electrode members including a first electrode member and a second electrode member, a thickness of the memory member at the position of the first electrode member being greater than a thickness of the memory member at the position of the second electrode member.
    Type: Application
    Filed: January 23, 2020
    Publication date: May 21, 2020
    Applicant: Toshiba Memory Corporation
    Inventor: Naoki Yasuda
  • Patent number: 10580786
    Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode members and a plurality of insulating members, each of the electrode members and each of the insulating members being stacked alternately in a first direction on the substrate. The semiconductor memory device also includes a memory hole that extends in the stacked body in the first direction and a semiconductor member that is disposed to extend in the memory hole in the first direction. The semiconductor memory device also includes a memory member that is disposed between the semiconductor member and the plurality of electrode members. The plurality of electrode members including a first electrode member and a second electrode member, a thickness of the memory member at the position of the first electrode member being greater than a thickness of the memory member at the position of the second electrode member.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: March 3, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Naoki Yasuda
  • Publication number: 20200060023
    Abstract: A power supply device (100-1) includes: a substrate (20) on which an electric component (25) is mounted; a chassis (10) including a chassis surface (11) to be a surface facing one surface (20a) of the substrate (20); and cured insulating resin (27-1) to be placed between the one surface (20a) of the substrate (20) and the chassis surface (11) so as to be connected to the one surface (20a) and the chassis surface (11), the cured insulating resin (27-1) having a thermal conductivity between 1 W/mK and 10 W/mK inclusive.
    Type: Application
    Filed: December 28, 2017
    Publication date: February 20, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Takashi MIYAMOTO, Naoki YASUDA, Shinichi OKADA, Hiroyuki OSUGA, Ryota KUSANO
  • Publication number: 20200032046
    Abstract: A curable composition (X) includes: an epoxy resin (A); a curing agent (B); a curing promoter (C); and hydrophilic inorganic particles (D). The epoxy resin (A) includes a first epoxy resin (a1) and a second epoxy resin (a2). The first epoxy resin (a1) is a chain aliphatic epoxy resin having a hydrophilic group, and an aqueous dissolution rate of the first epoxy resin (a1) is not less than 20 mass % and not more than 99 mass %. The second epoxy resin (a2) includes at least one selected from the group consisting of a cyclic aliphatic epoxy resin, an aromatic epoxy resin and a heterocyclic epoxy resin.
    Type: Application
    Filed: December 21, 2016
    Publication date: January 30, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Azusa OSAWA, Takahiro MABUCHI, Naoki YASUDA
  • Patent number: 10490395
    Abstract: An ICP analyzer 100 includes a self-oscillation radio-frequency power supply unit 120 for supplying radio-frequency power for generating plasma to an induction coil 111 wound around a plasma torch 110. To check the type of plasma torch 110, the analyzer 100 further includes: a frequency measurement section 121 for measuring an output frequency of the power supply unit 120; a storage unit 190 holding a reference output frequency for each type of plasma torch; and a torch checker 132 for determining whether or not the output frequency measured by the frequency measurement section 121 after the plasma is lit agrees with any one of the reference output frequencies, and for giving notification of the determination result.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: November 26, 2019
    Assignee: SHIMADZU CORPORATION
    Inventor: Naoki Yasuda
  • Patent number: 10347648
    Abstract: A nonvolatile semiconductor storage device having a control gate formed on a semiconductor substrate and including a cylindrical through hole. A block insulating film, a charge storage film, a tunnel insulating film, and a semiconductor layer are formed on a side surface of the control gate inside the through hole. The tunnel insulating film includes a first insulating film having SiO2 as a base material and containing an element that lowers a band gap of the base material by being added. A density and a density gradient of the element monotonously increase from the semiconductor layer toward the charge storage film.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: July 9, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Naoki Yasuda, Masaru Kito
  • Publication number: 20190144703
    Abstract: A coating material of the present invention includes an insulating resin, and dispersion particles dispersed in the insulating resin. The dispersion particle includes a core particle containing zinc oxide as a main component and having nonlinear resistance, and a resin layer covering the surface of the core particle and having an average thickness being less than or equal to 5.0 ?m. The coating material of the present invention is a coating material for coating an inner surface of a ground tank of a gas insulated switchgear.
    Type: Application
    Filed: April 6, 2017
    Publication date: May 16, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Satoru SATO, Naoki YASUDA, Nobuo YOKOMURA, Ryoko KAWANO, Manabu YOSHIMURA, Shinichiro NAKAUCHI
  • Patent number: 10283515
    Abstract: A semiconductor memory device includes a plurality of electrode layers stacked in a first direction; a semiconductor layer of a columnar shape extending through the electrode layers in the first direction; and a plurality of floating gates provided between the electrode layers and the semiconductor layer respectively. The floating gates surround the semiconductor layer. A gate length in a first direction of a floating gate positioned between one of the electrode layers and the semiconductor layer is longer than a layer thickness in the first direction of the one of the electrode layers. A ratio of the layer thickness of the one of the electrode layers to the gate length has a positive correlation with an outer diameter of a first portion of the semiconductor layer surrounded by the floating gate in a second direction from the semiconductor layer toward the one of the electrode layers.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: May 7, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Naoki Yasuda
  • Publication number: 20180258313
    Abstract: The present invention provides a solvent-free varnish composition, including: a thermosetting resin (A) having two or more (meth)acryloyl groups in a molecule thereof; a thermosetting resin (B) having one or more epoxy groups in a molecule thereof; a monofunctional vinyl-based monomer having an ether bond or an ester bond; an organic peroxide having a 10-hour half-life temperature of 40° C. or more; and a curing catalyst for an epoxy resin, in which a mixed resin of the thermosetting resin (A) and the thermosetting resin (B) has an epoxy equivalent of from 500 to 5,000. The solvent-free varnish composition can be used as an insulating varnish that shows a small energy loss and requires a short curing time in its curing treatment step, and that provides a cured product that barely causes the precipitation of an oligomer or the like even when exposed to a refrigerant-based environment containing a refrigerant and a refrigerating machine oil under high temperature and high pressure.
    Type: Application
    Filed: October 8, 2015
    Publication date: September 13, 2018
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Naoki YASUDA, Shigeyuki YAMAMOTO, Toshifumi KANRI, Takahiro TSUTSUMI, Masashi ONO, Kosuke SANO, Yukio HIDAKA
  • Publication number: 20180254279
    Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode members and a plurality of insulating members, each of the electrode members and each of the insulating members being stacked alternately in a first direction on the substrate. The semiconductor memory device also includes a memory hole that extends in the stacked body in the first direction and a semiconductor member that is disposed to extend in the memory hole in the first direction. The semiconductor memory device also includes a memory member that is disposed between the semiconductor member and the plurality of electrode members. The plurality of electrode members including a first electrode member and a second electrode member, a thickness of the memory member at the position of the first electrode member being greater than a thickness of the memory member at the position of the second electrode member.
    Type: Application
    Filed: May 1, 2018
    Publication date: September 6, 2018
    Applicant: Toshiba Memory Corporation
    Inventor: Naoki Yasuda
  • Publication number: 20180175048
    Abstract: A nonvolatile semiconductor storage device having a control gate formed on a semiconductor substrate and including a cylindrical through hole. A block insulating film, a charge storage film, a tunnel insulating film, and a semiconductor layer are formed on a side surface of the control gate inside the through hole. The tunnel insulating film includes a first insulating film having SiO2 as a base material and containing an element that lowers a band gap of the base material by being added. A density and a density gradient of the element monotonously increase from the semiconductor layer toward the charge storage film.
    Type: Application
    Filed: January 30, 2018
    Publication date: June 21, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Naoki YASUDA, Masaru KITO
  • Patent number: 9991274
    Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode members and a plurality of insulating members, each of the electrode members and each of the insulating members being stacked alternately in a first direction on the substrate. The semiconductor memory device also includes a memory hole that extends in the stacked body in the first direction and a semiconductor member that is disposed to extend in the memory hole in the first direction. The semiconductor memory device also includes a memory member that is disposed between the semiconductor member and the plurality of electrode members. The plurality of electrode members including a first electrode member and a second electrode member, a thickness of the memory member at the position of the first electrode member being greater than a thickness of the memory member at the position of the second electrode member.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: June 5, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Naoki Yasuda
  • Publication number: 20180138190
    Abstract: A semiconductor memory device includes a plurality of electrode layers stacked in a first direction; a semiconductor layer of a columnar shape extending through the electrode layers in the first direction; and a plurality of floating gates provided between the electrode layers and the semiconductor layer respectively. The floating gates surround the semiconductor layer. A gate length in a first direction of a floating gate positioned between one of the electrode layers and the semiconductor layer is longer than a layer thickness in the first direction of the one of the electrode layers. A ratio of the layer thickness of the one of the electrode layers to the gate length has a positive correlation with an outer diameter of a first portion of the semiconductor layer surrounded by the floating gate in a second direction from the semiconductor layer toward the one of the electrode layers.
    Type: Application
    Filed: December 26, 2017
    Publication date: May 17, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Naoki YASUDA
  • Patent number: 9953996
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, and a charge storage film. The stacked body is provided on the substrate. The stacked body includes a plurality of first insulating films and a plurality of electrode films alternately stacked one layer by one layer. The semiconductor pillar is provided inside the stacked body and extends in a stacking direction of the stacked body. The charge storage film is provided between the semiconductor pillar and each of the electrode films. The plurality of first insulating films include a first portion surrounding the semiconductor pillar and a second portion provided between the first portion and the semiconductor pillar, the second portion having a dielectric constant higher than a dielectric constant of the first portion.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: April 24, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Naoki Yasuda
  • Patent number: 9917095
    Abstract: A nonvolatile semiconductor storage device having a control gate formed on a semiconductor substrate and including a cylindrical through hole. A block insulating film, a charge storage film, a tunnel insulating film, and a semiconductor layer are formed on a side surface of the control gate inside the through hole. The tunnel insulating film includes a first insulating film having SiO2 as a base material and containing an element that lowers a band gap of the base material by being added. A density and a density gradient of the element monotonously increase from the semiconductor layer toward the charge storage film.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: March 13, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Naoki Yasuda, Masaru Kito