Patents by Inventor Naoki Yasuda

Naoki Yasuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080237688
    Abstract: A memory cell of a nonvolatile semiconductor memory includes a first insulating film whose principal constituent elements are Si, O and N, a charge storage layer whose principal constituent elements are Hf, O and N, formed on the first insulating film, a second insulating film having dielectric constant higher than that of the first insulating film and formed on the charge storage layer, and a control gate electrode formed on the second insulating film. Relation between a composition of the first insulating film and a composition of the charge storage layer is determined under the conditions that (A) a valence band offset of the first insulating film is larger than a valence band offset of the charge storage layer, and (B) a trap energy level of electrons due to oxygen vacancies in the charge storage layer exists within a band gap of the charge storage layer.
    Type: Application
    Filed: March 7, 2008
    Publication date: October 2, 2008
    Inventor: Naoki Yasuda
  • Patent number: 7399214
    Abstract: The step of forming an opening in an insulating layer to expose a carbon nanotube layer is performed using two types of dry etching different from each other in conditions. In the first-stage dry etching step, a hole is formed in the insulating layer to such a depth as not exposing the carbon nanotube layer. Thereafter, in the second-stage dry etching step, a bottom surface portion of the hole is removed, thus exposing an upper surface of the carbon nanotube layer. A method of manufacturing an electron emission source capable of improving performance of an electron emission portion is thus obtained.
    Type: Grant
    Filed: May 3, 2006
    Date of Patent: July 15, 2008
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kunihiko Nishimura, Naoki Yasuda, Yosuke Suzuki, Yoshinobu Hirokado, Satoru Kawamoto
  • Publication number: 20080073704
    Abstract: The present invention provides a nonvolatile semiconductor memory device including memory cells capable of electrically writing information, and each of the memory cells includes a first insulating film formed on the channel provided between source/drain diffusion layers, an electric charge accumulation layer formed on the first insulating film and is made of nitride or oxynitride containing at least one selected from Si, Ge, Ga, and Al, a donor layer containing n-type dopant impurity formed on the electric charge accumulation layer and is made of nitride or oxynitride containing at least one selected from among Si, Ge, Ga, and Al, a second insulating film formed on the donor layer, and a control gate electrode formed on the second insulating film.
    Type: Application
    Filed: July 9, 2007
    Publication date: March 27, 2008
    Inventor: Naoki Yasuda
  • Publication number: 20080038585
    Abstract: The present invention provides a method of manufacturing a film including the steps of using a compound with borazine skeleton (preferably a compound expressed by a chemical formula (1) below (where R1-R6 may be identical with or different from each other, and are each independently selected from a group consisting of a hydrogen atom, and an alkyl group, an alkenyl group and an alkynyl group each having a carbon number of 1-4, on condition that at least one of R1-R6 is not the hydrogen atom)) as a raw material, and forming the film on a substrate by using a chemical vapor deposition method, characterized in that a negative charge is applied to a site for placing the substrate, and a semiconductor device utilizing a film manufactured by the method.
    Type: Application
    Filed: October 7, 2005
    Publication date: February 14, 2008
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Teruhiko Kumada, Naoki Yasuda, Hideharu Nobutoki, Norihisa Matsumoto, Shigeru Matsuno
  • Publication number: 20080029027
    Abstract: The present invention provides a plasma CVD device including means for supplying a compound with borazine skeleton, a plasma generator for generating a plasma, and means for applying a negative charge to an electrode for placing a substrate. According to the present invention, it is possible to provide a plasma CVD device which stably provides a low dielectric constant and a high mechanical strength over a long period of time, reducing the amount of a gas component (outgas) emitted in heating the film, and causing no trouble in a device manufacturing process.
    Type: Application
    Filed: October 7, 2005
    Publication date: February 7, 2008
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Teruhiko Kumada, Naoki Yasuda, Hideharu Nobutoki, Norihisa Matsumoto, Shigeru Matsuno
  • Publication number: 20070284646
    Abstract: According to an aspect of the invention, a nonvolatile semiconductor memory device includes: a semiconductor layer comprising an n-type semiconductor region; p-type source-drain regions separated from each other within the n-type semiconductor region; a charge storage layer provided on the semiconductor layer and between the p-type source-drain regions, the charge storage layer comprising a high dielectric constant material; and a control gate electrode provided on the charge storage layer and comprising a material selected from n-type Si, a metal-based conductive material, and a p-type semiconductor material including at least one of Si and Ge.
    Type: Application
    Filed: March 23, 2007
    Publication date: December 13, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shoko Kikuchi, Naoki Yasuda, Koichi Muraoka, Yukie Nishikawa, Hirotaka Nishino
  • Publication number: 20070215929
    Abstract: A nonvolatile semiconductor memory device according to the embodiments of the invention includes a first insulating film on a channel, a floating gate electrode on the first insulating film, a second insulating film on the floating gate electrode, and a control gate electrode on the second insulating film. Each of the first and second insulating films comprises at least two layers, one layer directly in contact with the floating gate electrode is formed by an insulating material (A) including a metal element having a d-orbital, and the other at least one layer is formed by an insulating material (B) chiefly including one of a metal element without the d-orbital, and a semiconductor element.
    Type: Application
    Filed: March 1, 2007
    Publication date: September 20, 2007
    Inventor: Naoki YASUDA
  • Publication number: 20070132004
    Abstract: A nonvolatile semiconductor memory device according to an example of the present invention includes source/drain diffusion layers, a first insulation film on a channel between the source/drain diffusion layers, a floating gate electrode on the first insulation film and composed of first electrically conductive layers, a second insulation film on the floating gate electrode, and a control gate electrode on the second insulation film. In the case where one first electrically conductive layer excluding a top layer is defined as a reference layer among first electrically conductive layers, a work function of the reference layer is 4.0 eV or more and work functions of the reference layer and of the first electrically conductive layers above the reference layer gradually increase as the layers are proximal to the second insulation film.
    Type: Application
    Filed: October 12, 2006
    Publication date: June 14, 2007
    Inventors: Naoki YASUDA, Yukie NISHIKAWA, Koichi MURAOKA
  • Publication number: 20070072394
    Abstract: A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which injects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer based on information on the drawing pattern from a wafer testing part, information on the wafer from a storage part and coordinate information from a chip coordinate recognition part. In a semiconductor device manufacturing method according to the present invention, a semiconductor device is manufactured by using the semiconductor device manufacturing apparatus in such a manner that desired circuits are formed through printing process. In the semiconductor device, pad electrodes and so on are formed in such a way that trimming process can be conducted by printing circuit drawing patterns.
    Type: Application
    Filed: April 28, 2006
    Publication date: March 29, 2007
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Kazuhiro Shimizu, Hajime Akiyama, Naoki Yasuda
  • Publication number: 20070042547
    Abstract: A nonvolatile semiconductor memory device includes a tunnel insulating film, a floating gate electrode, an inter-electrode insulating film, and a control gate electrode. The tunnel insulating film is formed on a selected part of a surface of a semiconductor substrate. The floating gate electrode is formed on the tunnel insulating film. At least that interface region of the floating gate electrode, which is opposite to the substrate, is made of n-type Si or metal-based conductive material. The inter-electrode insulating film is formed on the floating gate electrode and made of high-permittivity material. The control gate electrode is formed on the inter-electrode insulating film. At least that interface region of the control gate electrode, which is on the side of the inter-electrode insulating film, is made of a p-type semiconductor layer containing at least one of Si and Ge.
    Type: Application
    Filed: May 15, 2006
    Publication date: February 22, 2007
    Inventors: Shoko Kikuchi, Naoki Yasuda, Koichi Muraoka, Yukie Nishikawa, Hirotaka Nishino
  • Publication number: 20060286814
    Abstract: There is provided a semiconductor device and method of fabricating the same that employs an insulation film of a borazine-based compound to provided enhanced contact between a material for insulation and that for interconnection, increased mechanical strength, and other improved characteristics. The semiconductor device includes a first insulation layer having a recess with a first conductor layer buried therein, an etching stopper layer formed on the first insulation layer, a second insulation layer formed on the etching stopper layer, a third insulation layer formed on the second insulation layer, and a second conductor layer buried in a recess of the second and third insulation layers. The second and third insulation layers are grown by chemical vapor deposition with a carbon-containing borazine compound used as a source material and the third insulation layer is smaller in carbon content than the second insulation layer.
    Type: Application
    Filed: June 14, 2006
    Publication date: December 21, 2006
    Applicant: Renesas Technology Corp.
    Inventors: Teruhiko Kumada, Hideharu Nobutoki, Naoki Yasuda, Kinya Goto, Masazumi Matsuura
  • Publication number: 20060258254
    Abstract: The step of forming an opening in an insulating layer to expose a carbon nanotube layer is performed using two types of dry etching different from each other in conditions. In the first-stage dry etching step, a hole is formed in the insulating layer to such a depth as not exposing the carbon nanotube layer. Thereafter, in the second-stage dry etching step, a bottom surface portion of the hole is removed, thus exposing an upper surface of the carbon nanotube layer. A method of manufacturing an electron emission source capable of improving performance of an electron emission portion is thus obtained.
    Type: Application
    Filed: May 3, 2006
    Publication date: November 16, 2006
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Kunihiko Nishimura, Naoki Yasuda, Yosuke Suzuki, Yoshinobu Hirokado, Satoru Kawamoto
  • Patent number: 6992363
    Abstract: A dielectric separation type semiconductor device having high voltage withstanding capability includes a primary dielectric layer (3-1) on a first surface of a semiconductor substrate (1), a first conductivity type first semiconductor layer (2) disposed oppositely to the substrate (1) with the primary dielectric layer (3-1) sandwiched, a first conductivity type second semiconductor layer (4) on the first semiconductor layer (2), a second conductivity type third semiconductor layer (5) surrounding peripherally the first semiconductor layer (2), a ring-like insulation film (9) surrounding peripherally the third semiconductor layer (5), a first electrode (6) on the second semiconductor layer (4), a second electrode (7) on the third semiconductor layer (5), a back-surface electrode (8) deposited on a second surface of the substrate (1), and a first auxiliary dielectric layer (3-2) disposed immediately below the second semiconductor layer (4), being junctioned to the second surface.
    Type: Grant
    Filed: July 7, 2003
    Date of Patent: January 31, 2006
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hajime Akiyama, Naoki Yasuda
  • Publication number: 20050240051
    Abstract: The invention provides a dispersant or a solubilizer containing a particular calixarene compound, wherein, of the phenolic hydroxyl groups constituting calixarene, at least one is not substituted, and at least one is substituted by a group having a total carbon number of not less than 10 and comprising one or more alkyleneoxy groups and/or a hydrocarbon group. A carbon-based material (fullerene, carbon nano tube and the like), an organic pigment (phthalocyanine blue and the like), and the like can be dispersed or solubilized in an organic matrix (organic solvent and the like) with the dispersant or solubilizer.
    Type: Application
    Filed: April 29, 2005
    Publication date: October 27, 2005
    Applicant: Ajinomoto Co., Inc.
    Inventors: Naoki Yasuda, Miho Furukawa
  • Publication number: 20050181628
    Abstract: A process for preparing a low dielectric constant material comprising heat-treating a compound containing a borazine skeleton structure of the formula: wherein at least one of R1 to R6 is a bond which binds said borazine skeleton structure to a molecule of a inorganic or organic compound, and/or R1 to R6 are independently a hydrogen atom, an alkyl group having 1 to 20 carbon atoms, an aryl group, a substituted aryl group, an alkenyl group, an amino group, an alkylamino group, an alkoxyl group, a thioalkoxyl group, a carbonyl group, a silyl group, an alkylsilyl group, a phosphino group, an alkylphosphino group or a group of the formula: Si(OR7)(OR8)(OR9), and at least one of R1 to R6 is not a hydrogen atom.
    Type: Application
    Filed: April 18, 2005
    Publication date: August 18, 2005
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hideharu Nobutoki, Teruhiko Kumada, Toshiyuki Toyoshima, Naoki Yasuda, Suguru Nagae
  • Publication number: 20050171247
    Abstract: The present invention provides a composition for wood-polymer composites containing a thermoplastic resin, wood flour and a polyol ester compound having not less than one hydroxyl group esterified with fatty acid, and a wood-polymer composite made from this composition. According to the present invention, a wood-polymer composite having well-balanced mechanical strength and processability, as compared to products made from lumber alone and products made from thermoplastic resin alone, and a composition for wood-polymer composites therefor can be provided.
    Type: Application
    Filed: March 31, 2005
    Publication date: August 4, 2005
    Applicant: Ajinomoto Co., Inc.
    Inventors: Naoki Yasuda, Haruo Nemoto
  • Patent number: 6924240
    Abstract: A low dielectric constant material having excellent water resistance comprising a borazine skeleton structure represented by any one of the formulas (2) to (4): wherein R1 to R4 are independently a hydrogen atom, an alkyl group having 1 to 20 carbon atoms, an aryl group, a substituted aryl group, an alkenyl group, an alkylamino group, an alkoxyl group, a thioalkoxyl group, a carbonyl group, a silyl group, an alkylsilyl group, a phosphino group, an alkyiphosphino group, or a group of the formula: Si(OR7)(OR8)(OR9), provided that at least one of R1 to R4 is not a hydrogen atom.
    Type: Grant
    Filed: October 9, 2002
    Date of Patent: August 2, 2005
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hideharu Nobutoki, Teruhiko Kumada, Toshiyuki Toyoshima, Naoki Yasuda, Suguru Nagae
  • Patent number: 6903149
    Abstract: The present invention provides a composition for wood-polymer composites containing a thermoplastic resin, wood flour and a polyol ester compound having not less than one hydroxyl group esterified with fatty acid, and a wood-polymer composite made from this composition. According to the present invention, a wood-polymer composite having well-balanced mechanical strength and processability, as compared to products made from lumber alone and products made from thermoplastic resin alone, and a composition for wood-polymer composites therefor can be provided.
    Type: Grant
    Filed: July 11, 2002
    Date of Patent: June 7, 2005
    Assignee: Ajinomoto Co., Inc.
    Inventors: Naoki Yasuda, Haruo Nemoto
  • Patent number: 6891368
    Abstract: A magnetoresistive sensor device including a substrate, and a sensing portion and a signal processing circuit formed above the substrate with a resin film being disposed between the sensing portion and the signal processing circuit. The sensing portion detects changes in a magnetic field induced by a moving body, is located at a position for effectively detecting changes in a magnetic field induced by the moving body, and is constituted by a magnetoresistive sensor element.
    Type: Grant
    Filed: November 5, 2002
    Date of Patent: May 10, 2005
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yuji Kawano, Naoki Yasuda, Motohisa Taguchi, Ikuya Kawakita, Shinichi Hosomi, Tatsuya Fukami
  • Patent number: D539634
    Type: Grant
    Filed: September 9, 2005
    Date of Patent: April 3, 2007
    Assignee: YKK AP Inc.
    Inventors: Hideoki Tanaka, Naoki Yasuda, Masashi Sugawara, Toru Kanai, Masaki Nomura