Patents by Inventor Naoki Yasui

Naoki Yasui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080182419
    Abstract: The invention provides a method for subjecting laminated thin films disposed below a photoresist mask pattern to plasma processing, wherein the roughness on the side walls of the formed pattern is reduced, and the LER and LWR are reduced. When etching a material to be processed to form a gate electrode including thin films such as a gate insulating film 205, a conducting layer 204, a mask layer 203 and an antireflection film 202 laminated on a semiconductor substrate 206 and a photoresist mask pattern 201 disposed on the antireflection film, prior to etching the mask pattern 201, plasma is generated from nitrogen gas or a mixed gas including nitrogen gas and deposition gas to subject the mask pattern 201 to a plasma curing process so as to reduce the roughness on the surface and side walls of the mask pattern 201, and then the laminated thin films 202, 203 and 204 disposed below the mask pattern 201 are subjected to a plasma etching process.
    Type: Application
    Filed: January 14, 2008
    Publication date: July 31, 2008
    Inventors: Naoki Yasui, Seiichi Watanabe
  • Patent number: 7373899
    Abstract: A plasma processing apparatus having a processing chamber connected to a vacuum exhauster so that its inside pressure can be reduced by the vacuum exhauster, a gas feed unit for supplying gas into the processing chamber, a substrate electrode provided in the processing chamber and on which a sample can be placed, an RF power supply connected through a matching circuit to the substrate electrode, plasma generating means for generating plasma within the processing chamber and a voltage waveform control circuit provided within the matching circuit or between the substrate electrode and the matching circuit to flatten the voltage waveform from the RF power supply.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: May 20, 2008
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Masahiro Sumiya, Naoki Yasui, Seiichi Watanabe, Hitoshi Tamura
  • Publication number: 20080023139
    Abstract: The invention relates to a plasma processing apparatus and a plasma processing method and particularly relates to a plasma processing apparatus suitable for executing an etching processing of a work by using plasma.
    Type: Application
    Filed: August 30, 2006
    Publication date: January 31, 2008
    Inventors: Naoki Yasui, Hiroho Kitada
  • Publication number: 20070218696
    Abstract: The invention provides a method for processing vertical gate patterns while reducing the Si substrate recess dimension caused by overetching. The invention provides a dry etching method for processing a gate pattern by performing a main etching process (b) and then an overetching process on a gate pattern layer 12 of a semiconductor substrate 10, wherein the overetching process (c) is performed using a composite gas having added to an etching gas containing HBr gas a gas represented by a general formula of CxHy or at least one gas selected from CO and CO2 gases.
    Type: Application
    Filed: August 25, 2006
    Publication date: September 20, 2007
    Inventors: Kenichi Kuwabara, Satoshi Une, Tomoyoshi Ichimaru, Masamichi Sakaguchi, Naoki Yasui
  • Publication number: 20070193976
    Abstract: The invention provides a plasma processing apparatus and a plasma processing method capable of controlling the voltage of the processing substrate with high accuracy, thereby enabling a highly accurate plasma processing. According to the invention, a voltage Vw of the processing substrate is measured using a processing substrate with a voltage probe prepared in advance, and based on a bias voltage Vesc applied to an electrostatic chuck mechanism 200 and a bias current Iesc flowing through the electrostatic chuck mechanism 200, a capacity component Cesc which is an impedance representing the electric property of the electrostatic chuck mechanism 200 is computed numerically. Then, based on a predetermined expression, the voltage Vw of the processing substrate 102 is estimated using the bias voltage Vesc of the processing substrate 102 to be measured, the bias current Iesc flowing through the electrostatic chuck mechanism 200 and the capacity component Cesc which is the impedance acquired in advance.
    Type: Application
    Filed: August 21, 2006
    Publication date: August 23, 2007
    Inventors: Hitoshi Tamura, Naoki Yasui, Seiichi Watanabe
  • Publication number: 20070186856
    Abstract: The plasma processing apparatus wherein the means for applying a high frequency voltage, which becomes a voltage waveform in which a positive constant voltage and a negative constant voltage alternate with each other at given cycles, is constituted by a DC power source and a switching circuit (a chopper circuit).
    Type: Application
    Filed: April 16, 2007
    Publication date: August 16, 2007
    Inventors: NAOKI YASUI, Seiichi Watanabe, Masahiro Sumiya, Hitoshi Tamura
  • Patent number: 7169255
    Abstract: A plasma processing apparatus for providing plasma processing to an object placed inside a processing chamber includes a vacuum chamber, a process gas feeder feeding gas into the vacuum chamber, a wafer electrode disposed within the vacuum chamber for mounting the object, a wafer bias power generator supplying bias voltage to the wafer electrode, and a plasma generator for generating plasma within the vacuum chamber. The wafer bias power generator includes a clip circuit for clipping either a positive-side voltage or a negative-side voltage to a predetermined voltage.
    Type: Grant
    Filed: February 6, 2003
    Date of Patent: January 30, 2007
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Naoki Yasui, Masahiro Sumiya, Hitoshi Tamura, Seiichi Watanabe
  • Patent number: 7029594
    Abstract: A plasma processing method for providing plasma processing to an object to be processed disposed within a vacuum processing chamber in which a process gas feeding device feeds process gas into the vacuum processing chamber, a wafer electrode is placed within the vacuum processing chamber for mounting the object to be processed, a wafer bias power generator applies self-bias voltage to the wafer electrode, and a plasma generator generates plasma within the vacuum processing chamber. The plasma processing method flattens either a positive side voltage or a negative side voltage of a voltage waveform of a high frequency voltage generated to the object at an arbitrary voltage.
    Type: Grant
    Filed: September 10, 2003
    Date of Patent: April 18, 2006
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Naoki Yasui, Masahiro Sumiya, Hitoshi Tamura, Seiichi Watanabe
  • Publication number: 20050155711
    Abstract: Processing technique using plasma to process the surface of a sample such as semiconductor device. The phases of RF bias voltages applied to a substrate electrode and an antenna electrode opposed thereto are controlled to be opposite to each other so that either one of the electrodes is forced to always function as ground. Accordingly, current flowing to cross the magnetic field for controlling the plasma is decreased, and the potential distribution difference in the surface of the sample to be processed is reduced, so that the charging damage can be suppressed. Energy of ions incident to the sample to be processed can be controlled to perform high-precision etching. The plasma potential can also be controlled so that the strength of the ion impact to the inner wall of the chamber can be reduced, thereby reducing particles detached from the inner wall of the processing apparatus to improve the throughput.
    Type: Application
    Filed: February 9, 2005
    Publication date: July 21, 2005
    Inventors: Masahiro Sumiya, Naoki Yasui, Seiichi Watanabe
  • Publication number: 20050126712
    Abstract: A plasma processing method utilizing an apparatus comprising a processing chamber to which is connected an exhaust pump for decompressing the chamber, a gas feeding apparatus for feeding gas into the processing chamber, an object to be processed, a wafer electrode for mounting the object, an antenna electrode for generating plasma and opposed to the plate electrode, a plasma generating high frequency power supply connected to the antenna electrode, a first high frequency power supply connected to the wafer electrode, and a second high frequency power supply connected to the antenna electrode. The method includes setting the high frequencies applied from the first high frequency power supply and the second high frequency power supply to be equal and controlling the phase of the respective high frequencies.
    Type: Application
    Filed: January 28, 2005
    Publication date: June 16, 2005
    Inventors: Masahiro Sumiya, Naoki Yasui, Tomoyuki Tamura
  • Publication number: 20050081999
    Abstract: A plasma processing apparatus suitable for high-speed and high-definition etching is provided. By applying to a wafer chucking electrode 9 a voltage waveform in which an absolute value of high frequency voltage increases with time and switching between a positive voltage and a negative voltage occurs, a rectangular high frequency voltage is caused to be generated in the wafer 10, with the result that the duty ratio of the rectangular high frequency voltage decreases and that the high energy ion ratio in the energy distribution of ions incident on the wafer increases. Therefore, high efficiency and high accuracy etching becomes possible, providing the advantage that the material selection ratio is improved.
    Type: Application
    Filed: March 9, 2004
    Publication date: April 21, 2005
    Inventors: Naoki Yasui, Seiichi Watanabe, Masahiro Sumiya, Hitoshi Tamura
  • Patent number: 6875366
    Abstract: Processing technique using plasma to process the surface of a sample such as semiconductor device. The phases of RF bias voltages applied to a substrate electrode and an antenna electrode opposed thereto are controlled to be opposite to each other so that either one of the electrodes is forced to always function as ground. Therefore, the current flowing to cross the magnetic field for controlling the plasma is decreased, and the potential distribution difference in the surface of the sample to be processed is reduced, so that the charging damage can be suppressed. Energy of ions incident to the sample to be processed can be controlled to perform high-precision etching. The plasma potential can also be controlled so that the strength of the ion impact to the inner wall of the chamber can be reduced, thereby reducing particles detached from the inner wall of the processing apparatus to improve the throughput.
    Type: Grant
    Filed: September 6, 2001
    Date of Patent: April 5, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Sumiya, Naoki Yasui, Seiichi Watanabe
  • Publication number: 20050034813
    Abstract: A plasma processing apparatus having a processing chamber connected to a vacuum exhauster so that its inside pressure can be reduced by the vacuum exhauster, a gas feed unit for supplying gas into the processing chamber, a substrate electrode provided in the processing chamber and on which a sample can be placed, an RF power supply connected through a matching circuit to the substrate electrode, plasma generating means for generating plasma within the processing chamber and a voltage waveform control circuit provided within the matching circuit or between the substrate electrode and the matching circuit to flatten the voltage waveform from the RF power supply.
    Type: Application
    Filed: September 30, 2004
    Publication date: February 17, 2005
    Inventors: Masahiro Sumiya, Naoki Yasui, Seiichi Watanabe, Hitoshi Tamura
  • Patent number: 6806201
    Abstract: A plasma processing method and apparatus are proposed that are suited to process the surface of a sample such as a semiconductor device using plasma. The bias voltages to the plasma generation and sample are respectively independently controlled, the RF voltage waveform as the bias voltage to a substrate electrode on which the sample is placed is flattened at an arbitrary voltage level, thereby controlling the energy distribution of ions incident to the sample to be a desired distribution. Therefore, plasma processing can be carried out with high precision.
    Type: Grant
    Filed: September 6, 2001
    Date of Patent: October 19, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Sumiya, Naoki Yasui, Seiichi Watanabe, Hitoshi Tamura
  • Publication number: 20040050495
    Abstract: A plasma processing apparatus comprising a processing chamber 102 to which is connected an exhaust pump 124 for decompressing the chamber, a gas feeding apparatus 107 for feeding gas into the processing chamber 102, an object 116 to be processed, a wafer electrode 115 for mounting the object 116, an antenna electrode 103 for generating plasma and opposed to the plate electrode 115, a plasma generating high frequency power supply 111 connected to the antenna electrode 103, a first high frequency power supply 119 connected to the wafer electrode 115, and a second high frequency power supply 114 connected to the antenna electrode 103, further comprising a phase control means 122 for controlling the phase difference of high frequencies applied from the first high frequency power supply 119 and the second high frequency power supply 114 and having the same frequency, according to which the phase of the high frequencies from the first and second power supplies are varied by 180°.
    Type: Application
    Filed: February 12, 2003
    Publication date: March 18, 2004
    Inventors: Masahiro Sumiya, Naoki Yasui, Tomoyuki Tamura
  • Publication number: 20040045673
    Abstract: A plasma processing method for providing plasma processing to an object to be processed disposed within a vacuum processing chamber in which a process gas feeding device feeds process gas into the vacuum processing chamber, a wafer electrode is placed within the vacuum processing chamber for mounting the object to be processed, a wafer bias power generator applies self-bias voltage to the wafer electrode, and a plasma generator generates plasma within the vacuum processing chamber. The plasma processing method flattens either a positive side voltage or a negative side voltage of a voltage waveform of a high frequency voltage generated to the object at an arbitrary voltage.
    Type: Application
    Filed: September 10, 2003
    Publication date: March 11, 2004
    Inventors: Naoki Yasui, Masahiro Sumiya, Hitoshi Tamura, Seiichi Watanabe
  • Publication number: 20030155075
    Abstract: The plasma processing apparatus for providing plasma processing to an object 114 placed inside a processing chamber 104 comprises a vacuum chamber 104, a process gas feeder 105 feeding gas into chamber 104, a wafer electrode 115 disposed within chamber 114 for mounting the object 114, a wafer bias power generator 117 supplying bias voltage to electrode 115, and a plasma generating means 112 for generating plasma within chamber 104, wherein said wafer bias power generator includes a clip circuit for clipping either the positive-side voltage or negative-side voltage to a predetermined voltage.
    Type: Application
    Filed: February 6, 2003
    Publication date: August 21, 2003
    Inventors: Naoki Yasui, Masahiro Sumiya, Hitoshi Tamura, Seiichi Watanabe
  • Publication number: 20020038631
    Abstract: A plasma processing method and apparatus are proposed that are suited to process the surface of a sample such as a semiconductor device using plasma. The bias voltages to the plasma generation and sample are respectively independently controlled, the RF voltage waveform as the bias voltage to a substrate electrode on which the sample is placed is flattened at an arbitrary voltage level, thereby controlling the energy distribution of ions incident to the sample to be a desired distribution. Therefore, plasma processing can be carried out with high precision.
    Type: Application
    Filed: September 6, 2001
    Publication date: April 4, 2002
    Inventors: Masahiro Sumiya, Naoki Yasui, Seiichi Watanabe, Hitoshi Tamura
  • Publication number: 20020031617
    Abstract: Processing technique using plasma to process the surface of a sample such as semiconductor device. The phases of RF bias voltages applied to a substrate electrode and an antenna electrode opposed thereto are controlled to be opposite to each other so that either one of the electrodes is forced to always function as ground. Therefore, the current flowing to cross the magnetic field for controlling the plasma is decreased, and the potential distribution difference in the surface of the sample to be processed is reduced, so that the charging damage can be suppressed. Energy of ions incident to the sample to be processed can be controlled to perform high-precision etching. The plasma potential can also be controlled so that the strength of the ion impact to the inner wall of the chamber can be reduced, thereby reducing particles detached from the inner wall of the processing apparatus to improve the throughput.
    Type: Application
    Filed: September 6, 2001
    Publication date: March 14, 2002
    Inventors: Masahiro Sumiya, Naoki Yasui, Seiichi Watanabe
  • Patent number: 5746695
    Abstract: A cap assembly of a front end of an inserting portion of an endoscope and a cap to be attached to the front end of the endoscope, comprising; a first engaging portion provided on the front end of the inserting portion of the endoscope; and, a second engaging portion provided on the cap being disengageably engaged with the first engaging portion of the endoscope. The front end of the inserting portion of the endoscope is provided with a projection whose diameter being smaller than a diameter of the front end, the projection being connected to the front end through a stepped portion.
    Type: Grant
    Filed: September 12, 1996
    Date of Patent: May 5, 1998
    Assignee: Asahi Kogaku Kogyo Kabushiki Kaisha
    Inventors: Naoki Yasui, Hiroshi Iwata, Hiroyuki Katsurada, Keiji Ito, Takayuki Ogino