Patents by Inventor Naoko Yamaguchi

Naoko Yamaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7486921
    Abstract: According to one mode of the present invention, a method of producing an electronic circuit, comprising forming an integrated resin layer having a prescribed thickness by repeating a resin layer forming process a number of times so that resin layers are layered to be integrated with all the resin layers on a substrate, wherein the resin forming process comprises charging the surface of a photoconductor; forming an electrostatic latent image having a prescribed pattern on the surface of the charged photoconductor; forming a visible image by electrostatically attaching charged particles composed of resin on the surface of the photoconductor on which the electrostatic latent image is formed; transferring the visible image formed on the surface of the photoconductor and composed of the charged particles onto the substrate; and fixing said visible image transferred onto said substrate on said substrate to form the resin layer on said substrate, is provided.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: February 3, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoko Yamaguchi, Hideo Aoki, Chiaki Takubo
  • Publication number: 20090007426
    Abstract: An image forming apparatus comprises an exposure unit forming an electrostatic latent image on a photo conductor based on image information, a developing unit developing the electrostatic latent image by toner made of formation material of a circuitry layer, and an electrostatic transferring unit transferring a toner image on the photo conductor onto a substrate. The toner image is transferred so as to cover at least a part of a conductor layer formed on the substrate. At this time, excessive charges caused in the conductor layer accompanying the start of the transfer of the toner image are removed. Alternatively, charges of which polarity is reverse to that of the toner are added to the conductor layer. These allow the circuitry layer to be formed to have a desired pattern favorably and securely on the conductor layer.
    Type: Application
    Filed: August 27, 2008
    Publication date: January 8, 2009
    Applicants: Kabushiki Kaisha Toshiba, Toshiba TEC Corporation
    Inventors: Hideo Aoki, Naoko Yamaguchi, Chiaki Takubo, Toshiaki Yamauchi, Koji Imamiya, Hiroshi Hashizume
  • Patent number: 7469941
    Abstract: A wiring board comprises a substrate; a resin layer which is selectively formed on one main surface of the substrate and has fine metal particles contained or adhered to its surface; and a conductive metal layer which is formed on the resin layer with the fine metal particles interposed between them.
    Type: Grant
    Filed: October 16, 2006
    Date of Patent: December 30, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideo Aoki, Chiaki Takubo, Naoko Yamaguchi
  • Patent number: 7433637
    Abstract: An image forming apparatus comprises an exposure unit forming an electrostatic latent image on a photoconductor based on image information, a developing unit developing the electrostatic latent image by toner made of formation material of a circuitry layer, and an electrostatic transferring unit transferring a toner image on the photoconductor onto a substrate. The toner image is transferred so as to cover at least a part of a conductor layer formed on the substrate. At this time, excessive charges caused in the conductor layer accompanying the start of the transfer of the toner image are removed. Alternatively, charges of which polarity is reverse to that of the toner are added to the conductor layer. These allow the circuitry layer to be formed to have a desired pattern favorably and securely on the conductor layer.
    Type: Grant
    Filed: April 7, 2005
    Date of Patent: October 7, 2008
    Assignees: Kabsushiki Kaisha Toshiba, Toshiba TEC Corporation
    Inventors: Hideo Aoki, Naoko Yamaguchi, Chiaki Takubo, Toshiaki Yamauchi, Koji Imamiya, Hiroshi Hashizume
  • Patent number: 7414417
    Abstract: According to one aspect of the invention, a contact sheet for testing electronic parts, comprising an insulating porous layer; and a connection electrode which is disposed on the insulating porous layer and electrically connect the electrode or terminal of the electronic parts and the terminal of a test apparatus; wherein the connection electrode is embedded below at least one main surface of the insulating porous layer.
    Type: Grant
    Filed: July 8, 2004
    Date of Patent: August 19, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoko Yamaguchi, Hideo Aoki, Chiaki Takubo, Toshiro Hiraoka, Yasuyuki Hotta, Shigeru Matake
  • Patent number: 7370412
    Abstract: An electronic device connecting method according to a first aspect of the present invention includes: mounting an electronic device having at least one electrode portion on a sheet-like porous member having a hole therein so that the electrode portion is close to the porous member; selectively irradiating a predetermined region of the porous member, on which the electronic device is mounted, with energy lines to form a latent image in an irradiated or non-irradiated portion of the porous member, the predetermined region including a portion close to the electrode portion; after irradiating with the energy lines, filling a conductive material in a hole of the latent image of the porous member to form a conductive portion; and bonding and integrating the porous member, in which the conductive portion is formed, to and with the electronic device.
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: May 13, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiro Hiraoka, Mitsuyoshi Endo, Naoko Yamaguchi, Yasuyuki Hotta, Shigeru Matake, Hideo Aoki, Misa Sawanobori
  • Patent number: 7350297
    Abstract: A first plating foundation layer is formed by printing on a front face of a sheet-shaped insulating substrate. By inserting a punch into the sheet-shaped insulating substrate having the first plating foundation layer, a through hole is formed while leaving a piece having the plating foundation layer in the portion where the punch is inserted. A second plating foundation layer is formed by printing on a rear face of the sheet-shaped insulating substrate. A first and second wiring layers composed of a metal plating layer are formed by performing electroless plating, and at the same time, a metal plating layer connecting between the first and second wiring layers is formed in the through hole using the plating foundation layer on the piece.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: April 1, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoko Yamaguchi, Hideo Aoki
  • Patent number: 7312621
    Abstract: A semiconductor test unit comprises a test circuit for inputting/outputting a test signal to/from an examined electronic product, a test signal wiring electrically connected to the test circuit, a contact board electrically connected to an electrode of the examined electronic product and provided with an electrically conductive via to which the test signal is transmitted, a multilayer circuit board electrically connected to the conductive via and the test signal wiring, located under the bottom face of the contact board, and provided with at least one through-hole, and a vacuum attachment mechanism for attaching thereto and holding the examined electronic product, the contact board, and the multilayer circuit board by vacuum. The contact board is made of an insulative material, has top and bottom faces, and is provided with at least one through-hole.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: December 25, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoko Yamaguchi, Yoshiaki Sugizaki, Hideo Aoki, Toshiro Hiraoka, Yasuyuki Hotta, Shigeru Matake, Misa Sawanobori
  • Patent number: 7259046
    Abstract: According to one aspect of the present invention, a semiconductor device, comprising a wiring board provided with wires and electrodes; a semiconductor element which is mounted on the wiring board and has plural connection electrodes formed on its surface; and a metal layer of fine metal particles aggregated and bonded which is interposed between the electrodes on the wiring board and the connection electrodes of the semiconductor element to connect between the electrodes and the connection electrodes, is provided.
    Type: Grant
    Filed: March 9, 2005
    Date of Patent: August 21, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideo Aoki, Yoshiaki Sugizaki, Naoko Yamaguchi, Chiaki Takubo
  • Publication number: 20070029107
    Abstract: A wiring board comprises a substrate; a resin layer which is selectively formed on one main surface of the substrate and has fine metal particles contained or adhered to its surface; and a conductive metal layer which is formed on the resin layer with the fine metal particles interposed between them.
    Type: Application
    Filed: October 16, 2006
    Publication date: February 8, 2007
    Inventors: Hideo Aoki, Chiaki Takubo, Naoko Yamaguchi
  • Publication number: 20060194031
    Abstract: A first plating foundation layer is formed by printing on a front face of a sheet-shaped insulating substrate. By inserting a punch into the sheet-shaped insulating substrate having the first plating foundation layer, a through hole is formed while leaving a piece having the plating foundation layer in the portion where the punch is inserted. A second plating foundation layer is formed by printing on a rear face of the sheet-shaped insulating substrate. A first and second wiring layers composed of a metal plating layer are formed by performing electroless plating, and at the same time, a metal plating layer connecting between the first and second wiring layers is formed in the through hole using the plating foundation layer on the piece.
    Type: Application
    Filed: February 17, 2006
    Publication date: August 31, 2006
    Inventors: Naoko Yamaguchi, Hideo Aoki
  • Patent number: 7067398
    Abstract: According to an embodiment of the present invention, a method of producing an electronic circuit comprises printing first metal-containing resin particles which consist of at least a thermosetting resin and fine metal particles and second metal-containing resin particles which consist of at least a thermoplastic resin and fine metal particles by electrophotography to form a first base pattern which consists of the first metal-containing resin particles and a second base pattern which consists of the second metal-containing resin particles on a substrate; forming a first metal conductor layer on the first and second base patterns; forming a second metal conductor layer on the first metal conductor layer by electrolytic plating by supplying electric current to the first metal conductor layer; and removing the second base pattern and the first and second metal conductor layers which are formed on the second base pattern.
    Type: Grant
    Filed: April 12, 2005
    Date of Patent: June 27, 2006
    Assignees: Kabushiki Kaisha Toshiba, Toshiba TEC Corporation
    Inventors: Hideo Aoki, Naoko Yamaguchi, Chiaki Takubo, Toshiaki Yamauchi, Koji Imamiya, Hiroshi Hashizume
  • Publication number: 20050279996
    Abstract: An organic semiconductor element comprises an organic semiconductor layer and an electrode supplying an electric current or an electric field to the organic semiconductor layer. The organic semiconductor layer includes a heat fusion layer of organic semiconductor particles. The heat fusion layer of the organic semiconductor particles is formed in such a manner that, for example, the organic semiconductor particles are made to adhere on a layer that is to be a base, by using an electrophotographic method, and thereafter, an adhesion layer of the organic semiconductor particles is heated to fusion bond the organic semiconductor particles. According to such an organic semiconductor element and a manufacturing method thereof, it is possible to enhance element manufacturing efficiency without an advantage of low cost and a miniaturization of an element structure.
    Type: Application
    Filed: June 15, 2005
    Publication date: December 22, 2005
    Inventors: Chiaki Takubo, Hideo Aoki, Naoko Yamaguchi
  • Patent number: 6977130
    Abstract: A method of manufacturing an electronic circuit satisfying demands for cost reduction, diversified small-quantity production, and a shorter cycle of design, manufacture, evaluation, correction, and so on is provided. The method includes at least forming a first pattern or forming a second pattern. Forming the first pattern comprises: forming a visible image on an electrostatic latent image formed on a photosensitive base, by the adhesion of charged particles essentially made of a resin; transferring the visible image onto the intermediate transfer base by the contact and pressurization of the visible image; heating/softening on the intermediate transfer base; and transferring a heated/softened resin layer onto a base material by the contact and pressurization of the resin layer.
    Type: Grant
    Filed: July 15, 2003
    Date of Patent: December 20, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideo Aoki, Chiaki Takubo, Atsuko Iida, Yasuyuki Hotta, Naoko Yamaguchi
  • Publication number: 20050255768
    Abstract: A nonwoven fabric characterized in that the nonwoven fabric is a thermoplastic synthetic fiber nonwoven fabric having a fabric weight of 7 to 50 g/m2, an average yarn diameter of 7 to 40 ?m, a partial heat contact bonding ratio of 5 to 30% and a content of a delustering agent of 0.5% by weight or less, or a nonwoven fabric laminate the major component of which is the thermoplastic synthetic fiber nonwoven fabric, and that the nonwoven fabric has a maximum opening diameter of 200 to 2,000 ?m, and shows a transparency of 50% or more, a powder leakage ratio of 10% by weight or less and a hydrophilicity of less than 10 sec, and a tea bag in which the nonwoven fabric is used.
    Type: Application
    Filed: June 24, 2003
    Publication date: November 17, 2005
    Inventors: Hirohumi Iwasaki, Hirohiko Nagao, Naoko Yamaguchi, Mitsunori Saito
  • Publication number: 20050227158
    Abstract: A conductive underlayer is formed in an electrophotographic manner using a toner comprising toner particles containing a binder resin containing a green thermosetting resin and conductive particles having an average particle diameter of 0.05 ?m to 1 ?m, wherein 50% by volume particle diameter of the toner is in a range 4 ?m to 12 ?m and the ratio of the toner with a size of 4 ?m or smaller is 20% by number or less, or a toner including external additives containing hydrophobic-treated small size metal oxide particles having a BET specific surface area of 150 m2/g to 400 m2/g and large size metal oxide particles having a BET specific surface area of 10 m2/g to 70 m2/g and then a conductive layer is formed thereon by plating.
    Type: Application
    Filed: March 16, 2005
    Publication date: October 13, 2005
    Inventors: Toshiaki Yamauchi, Koji Imamiya, Hiroshi Hashizume, Hideo Aoki, Naoko Yamaguchi, Chiaki Takubo
  • Publication number: 20050227161
    Abstract: An image forming apparatus comprises an exposure unit forming an electrostatic latent image on a photoconductor based on image information, a developing unit developing the electrostatic latent image by toner made of formation material of a circuitry layer, and an electrostatic transferring unit transferring a toner image on the photoconductor onto a substrate. The toner image is transferred so as to cover at least a part of a conductor layer formed on the substrate. At this time, excessive charges caused in the conductor layer accompanying the start of the transfer of the toner image are removed. Alternatively, charges of which polarity is reverse to that of the toner are added to the conductor layer. These allow the circuitry layer to be formed to have a desired pattern favorably and securely on the conductor layer.
    Type: Application
    Filed: April 7, 2005
    Publication date: October 13, 2005
    Inventors: Hideo Aoki, Naoko Yamaguchi, Chiaki Takubo, Toshiaki Yamauchi, Koji Imamiya, Hiroshi Hashizume
  • Publication number: 20050224253
    Abstract: A wiring board comprises a substrate; a resin layer which is selectively formed on one main surface of the substrate and has fine metal particles contained or adhered to its surface; and a conductive metal layer which is formed on the resin layer with the fine metal particles interposed between them.
    Type: Application
    Filed: April 12, 2005
    Publication date: October 13, 2005
    Inventors: Hideo Aoki, Chiaki Takubo, Naoko Yamaguchi
  • Publication number: 20050224931
    Abstract: According to an embodiment of the present invention, a method of producing an electronic circuit comprises printing first metal-containing resin particles which consist of at least a thermosetting resin and fine metal particles and second metal-containing resin particles which consist of at least a thermoplastic resin and fine metal particles by electrophotography to form a first base pattern which consists of the first metal-containing resin particles and a second base pattern which consists of the second metal-containing resin particles on a substrate; forming a first metal conductor layer on the first and second base patterns; forming a second metal conductor layer on the first metal conductor layer by electrolytic plating by supplying electric current to the first metal conductor layer; and removing the second base pattern and the first and second metal conductor layers which are formed on the second base pattern.
    Type: Application
    Filed: April 12, 2005
    Publication date: October 13, 2005
    Inventors: Hideo Aoki, Naoko Yamaguchi, Chiaki Takubo, Toshiaki Yamauchi, Koji Imamiya, Hiroshi Hashizume
  • Publication number: 20050199989
    Abstract: According to one aspect of the present invention, a semiconductor device, comprising a wiring board provided with wires and electrodes; a semiconductor element which is mounted on the wiring board and has plural connection electrodes formed on its surface; and a metal layer of fine metal particles aggregated and bonded which is interposed between the electrodes on the wiring board and the connection electrodes of the semiconductor element to connect between the electrodes and the connection electrodes, is provided.
    Type: Application
    Filed: March 9, 2005
    Publication date: September 15, 2005
    Inventors: Hideo Aoki, Yoshiaki Sugizaki, Naoko Yamaguchi, Chiaki Takubo