Patents by Inventor Naoto Hirano

Naoto Hirano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10336810
    Abstract: Disclosed herein are chimeric antigen receptors (CARs) comprising an intracellular segment comprising an interleukin receptor chain, a JAK-binding motif, a Signal Transducer and Activator of Transcription (STAT) 5 association motif and/or a CD3? intracellular signaling domain comprising an exogenous STAT3 association motif, as well as cells and 5 compositions comprising said CARs and uses thereof.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: July 2, 2019
    Assignees: University Health Network, Takara Bio Inc.
    Inventors: Shinya Tanaka, Naoto Hirano, Yuki Kagoya
  • Publication number: 20180037630
    Abstract: Disclosed herein are chimeric antigen receptors (CARs) comprising an intracellular segment comprising an interleukin receptor chain, a JAK-binding motif, a Signal Transducer and Activator of Transcription (STAT) 5 association motif and/or a CD3? intracellular signaling domain comprising an exogenous STAT3 association motif, as well as cells and 5 compositions comprising said CARs and uses thereof.
    Type: Application
    Filed: February 11, 2016
    Publication date: February 8, 2018
    Inventors: Shinya Tanaka, Naoto Hirano, Yuki Kagoya
  • Publication number: 20160340403
    Abstract: Provided is a method for determining a TCR polypeptide chain that can form a TCR specific for a peptide of interest. Also provided are methods and compositions for producing a cell expressing a T cell receptor (TCR) specific for a peptide of interest, methods and compositions for producing a TCR chain nucleic acid and/or pair of TCR chain polypeptides and/or nucleic acids encoding a TCR, a cell population comprising the cell harboring the nucleic acids encoding a TCR obtained by said method, and a method for treating a disorder comprising administering to the subject said cell population.
    Type: Application
    Filed: January 28, 2015
    Publication date: November 24, 2016
    Inventors: NAOTO HIRANO, MUNEHIDE NAKATSUGAWA, TOSHIKI OCHI
  • Patent number: 8241423
    Abstract: A semiconductor wafer for an epitaxial growth is disclosed comprising: a main face on which a vapor phase epitaxial layer grows; a back face provided on an opposite side of the wafer; a main chamfered part along a circumferential edge where the main face and a side face of the wafer meet; and a back chamfered part along a circumferential edge where the back face and the side face meet is provided. After a CVD layer formation process is conducted to form a layer at least on the back face and the back chamfered part, a machining process is conducted on the main face to remove a CVD layer at least partially formed thereon so as to polish the main face to a mirror finished surface with a maximum height of profile (Rz) not exceeding 0.3 ?m.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: August 14, 2012
    Assignee: Sumco Techxiv Corporation
    Inventors: Eisyun Ikubo, Naoto Hirano, Moritaka Iwasa
  • Patent number: 7955845
    Abstract: The invention relates to antigen-presenting cells having specificity against a selected antigen and methods for making the cells. The invention also relates to a method of selecting efficient antigen-presenting cells using reporter fusion constructs. The highly efficient antigen-presenting cells of the invention will provide a therapeutic strategy of modulating immune responses for a variety of diseases.
    Type: Grant
    Filed: May 20, 2004
    Date of Patent: June 7, 2011
    Assignee: Dana Farber Cancer Institute, Inc.
    Inventors: Naoto Hirano, Marcus Butler, Lee M. Nadler
  • Patent number: 7847481
    Abstract: Ribs for defining pixel cells are formed in the shape of a lattice, and sustain electrodes and scan electrodes are disposed near the ribs. The electrodes are spaced apart in each pixel cell, and the sustain electrode and the scan electrode are each cut away between pixel cells arranged in the row direction to provide each pixel cell with individually separated electrodes. In addition, between pixel cells adjacent to each other in the row direction, the sustain electrodes and the scan electrodes are connected to each other by means of a sustain-side bus electrode and a scan-side bus electrode, respectively. This makes it possible to provide a high luminous efficiency. Furthermore, each pixel cell is provided with a wide distance between the electrodes and thereby with a large effective opening portion. Thus, this provides only a small amount of reduction in intensity when the electrodes are spaced apart between the pixel cells arranged in the row direction in order to increase the luminous efficiency.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: December 7, 2010
    Assignee: Panasonic Corporation
    Inventors: Yoshio Sano, Nobumitsu Aibara, Yoshiaki Yanai, Toshiyuki Akiyama, Tetsumasa Okamoto, Kazuaki Yanagida, Hirokazu Tateno, Naoto Hirano, Yoshito Tanaka, Tadashi Nakamura, Keiji Nunomura
  • Patent number: 7781837
    Abstract: A method for forming a pattern of a stacked film, includes steps (a) to (e). The step (a) is forming sequentially a first base insulating film and a light shielding material on a transparent substrate. The step (b) is patterning the light shielding material to obtain a light shielding film with a first pattern. The step (c) is forming sequentially a second base insulating film, a semiconductor film and a first oxide film on a substrate. The step (d) is forming a resist pattern with a second pattern on the first oxide film. The step (e) is forming a pattern of a stacked film by dry etching the first oxide film and the semiconductor film, above the light shielding film. The stacked film includes the semiconductor film and the first oxide film. The dry etching includes an etching by using an etching gas and the resist pattern as a mask. The semiconductor film includes a taper angle which is controlled to be within predetermined range.
    Type: Grant
    Filed: October 23, 2007
    Date of Patent: August 24, 2010
    Assignee: NEC Corporation
    Inventors: Nobuya Seko, Hitoshi Shiraishi, Kenichi Hayashi, Naoto Hirano, Atsushi Yamamoto
  • Publication number: 20080224270
    Abstract: A semiconductor wafer for an epitaxial growth is disclosed comprising: a main face on which a vapor phase epitaxial layer grows; a back face provided on an opposite side of the wafer; a main chamfered part along a circumferential edge where the main face and a side face of the wafer meet; and a back chamfered part along a circumferential edge where the back face and the side face meet is provided. After a CVD layer formation process is conducted to form a layer at least on the back face and the back chamfered part, a machining process is conducted on the main face to remove a CVD layer at least partially formed thereon so as to polish the main face to a mirror finished surface with a maximum height of profile (Rz) not exceeding 0.3 ?m.
    Type: Application
    Filed: September 28, 2007
    Publication date: September 18, 2008
    Applicant: SUMCO TECHXIV CORPORATION
    Inventors: Eisyun Ikubo, Naoto Hirano, Moritaka Iwasa
  • Publication number: 20080084161
    Abstract: Ribs for defining pixel cells are formed in the shape of a lattice, and sustain electrodes and scan electrodes are disposed near the ribs. The electrodes are spaced apart in each pixel cell, and the sustain electrode and the scan electrode are each cut away between pixel cells arranged in the row direction to provide each pixel cell with individually separated electrodes. In addition, between pixel cells adjacent to each other in the row direction, the sustain electrodes and the scan electrodes are connected to each other by means of a sustain-side bus electrode and a scan-side bus electrode, respectively. This makes it possible to provide a high luminous efficiency. Furthermore, each pixel cell is provided with a wide distance between the electrodes and thereby with a large effective opening portion. Thus, this provides only a small amount of reduction in intensity when the electrodes are spaced apart between the pixel cells arranged in the row direction in order to increase the luminous efficiency.
    Type: Application
    Filed: October 31, 2007
    Publication date: April 10, 2008
    Applicants: NEC Corporation
    Inventors: Yoshio SANO, Nobumitsu Aibara, Yoshiaki Yanai, Toshiyuki Akiyama, Tetsumasa Okamoto, Kazuaki Yanagida, Hirokazu Tateno, Naoto Hirano, Yoshito Tanaka, Tadashi Nakamura, Keiji Nunomura
  • Patent number: 7354615
    Abstract: Disclosed herein are a process for producing mixed crystals of disodium 5?-guanylate and disodium 5?-inosinate which comprises precipitating mixed crystals of disodium 5?-guanylate and disodium 5?-inosinate (I+G mixed crystals) by adding an aqueous mixed solution of disodium 5?-guanylate and disodium 5?-inosinate and a hydrophilic organic solvent at the same time into a crystallization vessel in such manner that the ratio of the hydrophilic organic solvent to the liquid phase in the crystallization vessel is maintained in a range of 30 to 70 vol %, as well as such process for producing I+G mixed crystals wherein said producing of I+G mixed crystals is carried out by seeding crystallization wherein crystals of 5?-IMP2Na or/and I+G mixed crystals are used as seed crystals.
    Type: Grant
    Filed: July 19, 2002
    Date of Patent: April 8, 2008
    Assignee: Ajinomoto Co., Inc.
    Inventors: Toyokazu Kaneko, Yasuo Yonou, Naoto Hirano, Shigemitsu Abe, Kunihiko Toumori
  • Publication number: 20080048264
    Abstract: A method for forming a pattern of a stacked film, includes steps (a) to (e). The step (a) is forming sequentially a first base insulating film and a light shielding material on a transparent substrate. The step (b) is patterning the light shielding material to obtain a light shielding film with a first pattern. The step (c) is forming sequentially a second base insulating film, a semiconductor film and a first oxide film on a substrate. The step (d) is forming a resist pattern with a second pattern on the first oxide film. The step (e) is forming a pattern of a stacked film by dry etching the first oxide film and the semiconductor film, above the light shielding film. The stacked film includes the semiconductor film and the first oxide film. The dry etching includes an etching by using an etching gas and the resist pattern as a mask. The semiconductor film includes a taper angle which is controlled to be within predetermined range.
    Type: Application
    Filed: October 23, 2007
    Publication date: February 28, 2008
    Applicant: NEC Corporation
    Inventors: Nobuya Seko, Hitoshi Shiraishi, Kenichi Hayashi, Naoto Hirano, Atsushi Yamamoto
  • Patent number: 7336033
    Abstract: Ribs for defining pixel cells are formed in the shape of a lattice, and sustain electrodes and scan electrodes are disposed near the ribs. The electrodes are spaced apart in each pixel cell, and the sustain electrode and the scan electrode are each cut away between pixel cells arranged in the row direction to provide each pixel cell with individually separated electrodes. In addition, between pixel cells adjacent to each other in the row direction, the sustain electrodes and the scan electrodes are connected to each other by means of a sustain-side bus electrode and a scan-side bus electrode, respectively. This makes it possible to provide a high luminous efficiency. Furthermore, each pixel cell is provided with a wide distance between the electrodes and thereby with a large effective opening portion. Thus, this provides only a small amount of reduction in intensity when the electrodes are spaced apart between the pixel cells arranged in the row direction in order to increase the luminous efficiency.
    Type: Grant
    Filed: October 14, 2005
    Date of Patent: February 26, 2008
    Assignee: Pioneer Corporation
    Inventors: Yoshio Sano, Nobumitsu Aibara, Yoshiaki Yanai, Toshiyuki Akiyama, Tetsumasa Okamoto, Kazuaki Yanagida, Hirokazu Tateno, Naoto Hirano, Yoshito Tanaka, Tadashi Nakamura, Keiji Nunomura
  • Patent number: 7317227
    Abstract: A semiconductor film serving as an active region of a thin film transistor and an upper oxide film protecting the semiconductor film are dry etched to form the active region. In this case, a fluorine-based gas is used as the etching gas, and the etching gas is switched from the fluorine-based gas to a chlorine-based gas at a point of time when a lower oxide film as an underlying film of the semiconductor film is exposed. As the fluorine-based gas, a mixed gas of CF4 and O2 is used, and suitably, a gas ratio of CF4 and O2 in the mixture gas is set at 1:1, and the dry etching is performed therefor. By this etching, a side face of a two-layer structure of the semiconductor film and upper oxide film is optimally tapered, and a crack or a disconnection is prevented from being occurring in a film crossing over the two-layer structure.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: January 8, 2008
    Assignee: NEC Corporation
    Inventors: Hitoshi Shiraishi, Kenichi Hayashi, Naoto Hirano, Atsushi Yamamoto
  • Patent number: 7303945
    Abstract: A method for forming a pattern of a stacked film, includes steps (a) to (e). The step (a) is forming sequentially a first base insulating film and a light shielding material on a transparent substrate. The step (b) is patterning the light shielding material to obtain a light shielding film with a first pattern. The step (c) is forming sequentially a second base insulating film, a semiconductor film and a first oxide film on a substrate. The step (d) is forming a resist pattern with a second pattern on the first oxide film. The step (e) is forming a pattern of a stacked film by dry etching the first oxide film and the semiconductor film, above the light shielding film. The stacked film includes the semiconductor film and the first oxide film. The dry etching includes an etching by using an etching gas and the resist pattern as a mask. The semiconductor film includes a taper angle which is controlled to be within predetermined range.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: December 4, 2007
    Assignee: NEC Corporation
    Inventors: Nobuya Seko, Hitoshi Shiraishi, Kenichi Hayashi, Naoto Hirano, Atsushi Yamamoto
  • Publication number: 20060220014
    Abstract: To provide a liquid crystal display device in which capacity value of storage capacitance is large and manufacturing cost is low, and a manufacturing method thereof. A plurality of gate lines is provided on a pixel circuit substrate of a liquid crystal display device. Further, a TFT is provided to each pixel, and a drain line is connected with the drain, and a pixel electrode is connected with the source, and the gate line is connected with the gate electrode. Lower electrodes are made to extend from the gate line. In an area immediately above the lower electrodes connected with the nth gate line from the drain line control circuit side, a pixel electrode coupled to the (n+1)th gate line via the TFT is disposed. Thereby, storage capacitance is formed between the lower electrodes connected with the nth gate line and the pixel electrode coupled to the (n+1)th gate line.
    Type: Application
    Filed: March 15, 2006
    Publication date: October 5, 2006
    Inventors: Naoto Hirano, Daisuke Iga, Kazuhide Yoshinaga
  • Patent number: 7002296
    Abstract: Ribs for defining pixel cells are formed in the shape of a lattice, and sustain electrodes and scan electrodes are disposed near the ribs. The electrodes are spaced apart in each pixel cell, and the sustain electrode and the scan electrode are each cut away between pixel cells arranged in the row direction to provide each pixel cell with individually separated electrodes. In addition, between pixel cells adjacent to each other in the row direction, the sustain electrodes and the scan electrodes are connected to each other by means of a sustain-side bus electrode and a scan-side bus electrode, respectively. This makes it possible to provide a high luminous efficiency.
    Type: Grant
    Filed: July 23, 2001
    Date of Patent: February 21, 2006
    Assignee: Pioneer Corporation
    Inventors: Yoshio Sano, Nobumitsu Aibara, Yoshiaki Yanai, Toshiyuki Akiyama, Tetsumasa Okamoto, Kazuaki Yanagida, Hirokazu Tateno, Naoto Hirano, Yoshito Tanaka, Tadashi Nakamura, Keiji Nunomura
  • Publication number: 20060033436
    Abstract: Ribs for defining pixel cells are formed in the shape of a lattice, and sustain electrodes and scan electrodes are disposed near the ribs. The electrodes are spaced apart in each pixel cell, and the sustain electrode and the scan electrode are each cut away between pixel cells arranged in the row direction to provide each pixel cell with individually separated electrodes. In addition, between pixel cells adjacent to each other in the row direction, the sustain electrodes and the scan electrodes are connected to each other by means of a sustain-side bus electrode and a scan-side bus electrode, respectively. This makes it possible to provide a high luminous efficiency. Furthermore, each pixel cell is provided with a wide distance between the electrodes and thereby with a large effective opening portion. Thus, this provides only a small amount of reduction in intensity when the electrodes are spaced apart between the pixel cells arranged in the row direction in order to increase the luminous efficiency.
    Type: Application
    Filed: October 14, 2005
    Publication date: February 16, 2006
    Inventors: Yoshio Sano, Nobumitsu Aibara, Yoshiaki Yanai, Toshiyuki Akiyama, Tetsumasa Okamoto, Kazuaki Yanagida, Hirokazu Tateno, Naoto Hirano, Yoshito Tanaka, Tadashi Nakamura, Keiji Nunomura
  • Patent number: 6933241
    Abstract: A semiconductor film serving as an active region of a thin film transistor and an upper oxide film protecting the semiconductor film are dry etched to form the active region. In this case, a fluorine-based gas is used as the etching gas, and the etching gas is switched from the fluorine-based gas to a chlorine-based gas at a point of time when a lower oxide film as an underlying film of the semiconductor film is exposed. As the fluorine-based gas, a mixed gas of CF4 and O2 is used, and suitably, a gas ratio of CF4 and O2 in the mixture gas is set at 1:1, and the dry etching is performed therefor. By this etching, a side face of a two-layer structure of the semiconductor film and upper oxide film is optimally tapered, and a crack or a disconnection is prevented from being occurring in a film crossing over the two-layer structure.
    Type: Grant
    Filed: May 29, 2003
    Date of Patent: August 23, 2005
    Assignee: NEC Corporation
    Inventors: Hitoshi Shiraishi, Kenichi Hayashi, Naoto Hirano, Atsushi Yamamoto
  • Publication number: 20050156239
    Abstract: A method for forming a pattern of a stacked film, includes steps (a) to (e). The step (a) is forming sequentially a first base insulating film and a light shielding material on a transparent substrate. The step (b) is patterning the light shielding material to obtain a light shielding film with a first pattern. The step (c) is forming sequentially a second base insulating film, a semiconductor film and a first oxide film on a substrate. The step (d) is forming a resist pattern with a second pattern on the first oxide film. The step (e) is forming a pattern of a stacked film by dry etching the first oxide film and the semiconductor film, above the light shielding film. The stacked film includes the semiconductor film and the first oxide film. The dry etching includes an etching by using an etching gas and the resist pattern as a mask. The semiconductor film includes a taper angle which is controlled to be within predetermined range.
    Type: Application
    Filed: November 30, 2004
    Publication date: July 21, 2005
    Applicant: NEC Corporation
    Inventors: Nobuya Seko, Hitoshi Shiraishi, Kenichi Hayashi, Naoto Hirano, Atsushi Yamamoto
  • Publication number: 20050003484
    Abstract: The invention relates to antigen-presenting cells having specificity against a selected antigen and methods for making the cells. The invention also relates to a method of selecting efficient antigen-presenting cells using reporter fusion constructs. The highly efficient antigen-presenting cells of the invention will provide a therapeutic strategy of modulating immune responses for a variety of diseases.
    Type: Application
    Filed: May 20, 2004
    Publication date: January 6, 2005
    Inventors: Naoto Hirano, Marcus Butler, Lee Nadler