Patents by Inventor Naoto Hirano

Naoto Hirano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6222600
    Abstract: In a reflective liquid crystal apparatus, a drain electrode and a source electrode are formed on a insulating substrate and are formed by an aluminum alloy layer. The source electrode serves as a light reflecting pixel electrode. Also, a non-doped semiconductor layer is formed on a part of the drain electrode and a part of the source electrode, and impurity-doped semiconductor layers are formed between the drain and source electrodes and the non-doped semiconductor layer. Further, a gate electrode is formed via a gate insulating layer on the non-doped semiconductor layer. Additionally, a counter common electrode is formed on a transparent insulating substrate, and a liquid crystal layer is interposed between the insulating substrate and the transparent insulating substrate.
    Type: Grant
    Filed: July 27, 2000
    Date of Patent: April 24, 2001
    Assignee: NEC Corporation
    Inventor: Naoto Hirano
  • Patent number: 6060302
    Abstract: Genes encoding a human PLC-.alpha. polypeptide are provided. An expression vector containing these genes and a transformant having the expression vector are provided. The human PLC-.alpha. polypeptide can be produced by cultivating the transformant. The human PLC-.alpha. polypeptide is useful as an anti-inflammatory agent. Furthermore, a measurement system for conducting clinical evaluation of canceration can be constructed by using the PLC-.alpha. polypeptide.
    Type: Grant
    Filed: March 22, 1996
    Date of Patent: May 9, 2000
    Assignees: Shionogi & Co., Ltd., Naoto Hirano
    Inventors: Naoto Hirano, Hisamaru Hirai
  • Patent number: 5652159
    Abstract: In a method of manufacturing a thin film transistor, a light shielding gate electrode is formed on a transparent insulating substrate. On the substrate including the gate electrode are laminated a gate insulating film, a semiconductor film, a protection insulating film, and a photoresist film. The photoresist film is patterned in alignment with the gate electrode. The protection insulating film is isotropically etched using the patterned photoresist film as a mask to have inclined portions. After the surface of the semiconductor film is rinsed to remove a natural oxide film, a metal film is deposited to form a metal silicide layer in alignment with the patterned protection insulating film. The metal film is patterned in such a manner that the metal portions are separated from the patterned protection insulating film.
    Type: Grant
    Filed: October 26, 1995
    Date of Patent: July 29, 1997
    Assignee: NEC Corporation
    Inventor: Naoto Hirano