Patents by Inventor Naoya Kanda

Naoya Kanda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060244121
    Abstract: Cut pieces of a flexible tape respectively having positioning holes are superposed on a substrate having positioning holes, while positioning the substrate and the cut pieces by inserting a positioning pin into the positioning holes respectively, so that one side of the substrate faces one side of the cut pieces. Subsequently, internal terminals provided on the substrate are ultrasonically joined with internal terminals provided on the cut pieces by pressing an ultrasonic tool from the other side of the cut pieces. As a result, connection between these can be performed highly accurately. Further, since the internal terminals are ultrasonically joined with each other, operation time does not increase in proportion to the number of terminals, as in the connection using a bonding wire, and misregistration due to heat does not occur. Accordingly, connections between circuit boards are performed efficiently, highly accurately, and reliably.
    Type: Application
    Filed: April 28, 2006
    Publication date: November 2, 2006
    Inventors: Masanori Shibamoto, Masahiro Yamaguchi, Naoya Kanda
  • Patent number: 7122087
    Abstract: There is a method of manufacturing an RFID, in which a semiconductor chip with a memory is bonded to an antenna, so that the information recorded in the memory can be transmitted through the antenna. In the RFID, a PET film, a PEN film, or a sheet of paper is used as the base material of the antenna. The method includes: aligning the semiconductor chip with gold bumps relative to the antenna, in which a metal foil formed of an aluminum or an aluminum alloy is adhered to the base material, including a polyethylene terephthalate or a polyethylene naphthalate; pressing the semiconductor chip to the antenna; and applying ultrasonic waves under an ambient temperature lower than the glass transition temperature of the polyethylene terephthalate or the polyethylene naphthalate, to thereby bond the gold bumps and the metal foil. Thus, the method suppresses the deformation of the antenna.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: October 17, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Naoya Kanda, Kosuke Inoue, Madoka Minagawa, Shigeharu Tsunoda
  • Patent number: 7084498
    Abstract: A semiconductor device which includes a semiconductor chip, an insulating film formed on the semiconductor chip, a plurality of projected stress relaxation materials formed on the insulating film, projected electrodes covering at least tops of the stress relaxation materials, and wiring lines for electrically connecting the projected electrodes and element electrodes of the semiconductor chip.
    Type: Grant
    Filed: October 17, 2002
    Date of Patent: August 1, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Yoshihide Yamaguchi, Shigeharu Tsunoda, Hiroyuki Tenmei, Hiroshi Hozoji, Naoya Kanda
  • Patent number: 7057283
    Abstract: A semiconductor apparatus in which flip chip bonding is enabled without any underfill, and which comprises a semiconductor device, an electrically insulating layer formed on the semiconductor device by mask-printing an electrically insulating material containing particles, and an external connection terminal formed on the electrically insulating layer and electrically connected with an electrode of the semiconductor device. The electrically insulating layer is formed with a thickness so as to provide ?-ray shielding of the semiconductor device.
    Type: Grant
    Filed: April 16, 2004
    Date of Patent: June 6, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Kosuke Inoue, Hiroyuki Tenmei, Yoshihide Yamaguchi, Noriyuki Oroku, Hiroshi Hozoji, Shigeharu Tsunoda, Madoka Minagawa, Naoya Kanda, Ichiro Anjo, Asao Nishimura, Akira Yajima, Kenji Ujiie
  • Patent number: 7002250
    Abstract: A semiconductor module, comprising a wiring substrate on which wiring is formed, a semiconductor device electrically connected to the wiring formed on the wiring substrate, and an external connection terminal arranged on the semiconductor device mounted side of the wiring substrate so as to be a connected portion between the wiring and the outside electrically connected thereto, wherein there is formed an insulating resin layer thicker than the semiconductor device between the wiring substrate and the external connection terminal.
    Type: Grant
    Filed: August 16, 2001
    Date of Patent: February 21, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Hiroshi Hozoji, Yoshihide Yamaguchi, Naoya Kanda, Shigeharu Tunoda, Hiroyuki Tenmei
  • Publication number: 20050230791
    Abstract: When an RFID-tag is formed by joining a semiconductor chip (RFID chip) to an antenna consisting of a rolled metal foil or the like using ultrasonic waves, the pressure impressed to the semiconductor chip is suppressed to avoid the damage of the semiconductor chip. For this purpose, the present invention provides an RFID-tag 1 wherein gold bumps are joined to the metal foil by pressing the gold bumps formed on the semiconductor chip against an antenna member, and impressing ultrasonic waves; and the RFID-tag wherein a matte surface having a low glossiness is formed on the metal foil, or a surface having shallow rolling streaks is formed on the metal foil, and gold bumps are joined to the surface.
    Type: Application
    Filed: March 10, 2005
    Publication date: October 20, 2005
    Inventors: Naoya Kanda, Madoka Minagawa, Kosuke Inoue, Hiroshi Homma
  • Patent number: 6930388
    Abstract: A semiconductor device is provided which enables a flip chip connection without use of underfill. The semiconductor device includes a semiconductor element having circuit electrodes and a circuit surface coated with a protecting film. A stress relaxation layer is provided by coating a cured thermoplastic resin onto the protecting film of the circuit surface in a manner which leaves the circuit electrodes exposed and curing it and having an inclination in the edge portion thereof. A wiring layer with wirings is connected to each of the circuit electrodes and disposed so as to make an electrical connection from the circuit electrodes, via the edge portion of the stress relaxation layer, and to a desired portion on the surface of the stress relaxation layer. A protecting film is provided thereon, and an external connection terminal is also provided.
    Type: Grant
    Filed: March 20, 2001
    Date of Patent: August 16, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Yoshihide Yamaguchi, Hiroyuki Tenmei, Kosuke Inoue, Noriyuki Oroku, Hiroshi Hozoji, Shigeharu Tsunoda, Naoya Kanda, Madoka Minagawa, Ichiro Anjo, Asao Nishimura, Kenji Ujiie, Akira Yajima
  • Publication number: 20050173541
    Abstract: A paper-like RFID tag is fabricated by bonding bumps of an RFID chip to an antenna to connect the chip to the antenna, the antenna being formed by a metal foil bonded onto a base film or a base tape, providing a protecting material around the RFID chip so that an upper surface becomes higher than that of the RFID chip, to constitute an RFID thread, and inlaying the RFID thread in between first and second paper layers to afford a paper-like structure. The thickness of the paper-like RFID tag fabricated as above is 0.1 mm or less. Further, the paper-like RFID tag is of high quality and has a surface smoothness almost equal to that of the ordinary type of paper, permitting a long-distance communication.
    Type: Application
    Filed: December 6, 2004
    Publication date: August 11, 2005
    Inventors: Kosuke Inoue, Naoya Kanda, Hiroshi Honma
  • Publication number: 20050130425
    Abstract: There is a method of manufacturing an RFID, in which a semiconductor chip with a memory is bonded to an antenna, so that the information recorded in the memory can be transmitted through the antenna. In the RFID, a PET film, a PEN film, or a sheet of paper is used as the base material of the antenna. The method includes: aligning the semiconductor chip with gold bumps relative to the antenna, in which a metal foil formed of an aluminum or an aluminum alloy is adhered to the base material, including a polyethylene terephthalate or a polyethylene naphthalate; pressing the semiconductor chip to the antenna; and applying ultrasonic waves under an ambient temperature lower than the glass transition temperature of the polyethylene terephthalate or the polyethylene naphthalate, to thereby bond the gold bumps and the metal foil. Thus, the method suppresses the deformation of the antenna.
    Type: Application
    Filed: November 12, 2004
    Publication date: June 16, 2005
    Inventors: Naoya Kanda, Kosuke Inoue, Madoka Minagawa, Shigeharu Tsunoda
  • Publication number: 20050085010
    Abstract: A highly reliable inexpensive RFID medium (Radio-frequency Identification medium) and a method of manufacturing the same is provided, particularly for small, thin RFID mediums. A RFID medium includes a transmitting/receiving antenna 2 and an IC chip 3. A rectangular part of a base sheet 1, having a major surface on which transmitting/receiving antennas 2 are formed, is folded along one of the long sides thereof, and the other three sides are bonded to the base sheet 1 so as to cover the transmitting/receiving antenna 2 and the IC chip 3 connected to the transmitting/receiving antenna 2. The base sheet 1 has spacing parts of a predetermined shape for covering the transmitting/receiving antenna 2 and the IC chip 3 connected to the transmitting/receiving antenna 2. The transmitting/receiving antennas 2 and the spacing parts 22 are arranged alternately. The base sheet 1 is rolled in a roll.
    Type: Application
    Filed: October 7, 2004
    Publication date: April 21, 2005
    Inventors: Shigeharu Tsunoda, Naoya Kanda
  • Patent number: 6822317
    Abstract: A semiconductor apparatus comprising a semiconductor device, an electrically insulating layer formed on the semiconductor device, and an external connection terminal formed on the electrically insulating layer and electrically connected to an electrode of the semiconductor device, wherein a power/ground line and a signal line in a region of from an edge of the electrically insulating layer to a uniform-thickness flat portion of the electrically insulating layer are different in kind of wiring pattern from each other.
    Type: Grant
    Filed: October 30, 2000
    Date of Patent: November 23, 2004
    Assignee: Renesas Technology Corporation
    Inventors: Kosuke Inoue, Hiroyuki Tenmei, Yoshihide Yamaguchi, Noriyuki Oroku, Hiroshi Hozoji, Shigeharu Tsunoda, Madoka Minagawa, Naoya Kanda, Ichiro Anjo, Asao Nishimura, Akira Yajima, Kenji Ujiie
  • Publication number: 20040195687
    Abstract: A semiconductor apparatus in which flip chip bonding is enabled without any underfill, and which comprises a semiconductor device, an electrically insulating layer formed on the semiconductor device by mask-printing an electrically insulating material containing particles, and an external connection terminal formed on the electrically insulating layer and electrically connected with an electrode of the semiconductor device. The electrically insulating layer is formed with a thickness so as to provide &agr;-ray shielding of the semiconductor device.
    Type: Application
    Filed: April 16, 2004
    Publication date: October 7, 2004
    Inventors: Kosuke Inoue, Hiroyuki Tenmei, Yoshihide Yamaguchi, Noriyuki Oroku, Hiroshi Hozoji, Shigeharu Tsunoda, Madoka Minagawa, Naoya Kanda, Ichiro Anjo, Asao Nishimura, Akira Yajima, Kenji Ujiie
  • Patent number: 6791178
    Abstract: A multi-chip module has semiconductor devices and a wiring substrate for mounting the semiconductor devices, in which the wiring substrate comprises a glass substrate having holes formed by sand blasting and a wiring layer formed on the surface of the glass substrate and having wiring and an insulation layer.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: September 14, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Yoshihide Yamaguchi, Takao Terabayashi, Hiroyuki Tenmei, Hiroshi Hozoji, Naoya Kanda
  • Patent number: 6780748
    Abstract: In the re-wiring formation process of a WLCSP, at least some of the re-wiring lines 3 that connect the bonding pads 1 and bump pads 2 of the semiconductor chips are formed using a photolithographic process that does not use a photomask. In this re-wiring formation process, standard portions are formed by development following photomask exposure, and portions that are to be designed corresponding to customer specifications are subjected to additional development following additional maskless exposure in the final stage.
    Type: Grant
    Filed: July 30, 2002
    Date of Patent: August 24, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Yoshihide Yamaguchi, Hiroyuki Tenmei, Hiroshi Hozoji, Naoya Kanda
  • Patent number: 6770547
    Abstract: A semiconductor apparatus in which flip chip bonding is enabled without any underfill, and which comprises a semiconductor device, an electrically insulating layer formed on the semiconductor device by mask-printing an electrically insulating material containing particles, and an external connection terminal formed on the electrically insulating layer and electrically connected with an electrode of the semiconductor device.
    Type: Grant
    Filed: October 30, 2000
    Date of Patent: August 3, 2004
    Assignee: Renesas Technology Corporation
    Inventors: Kosuke Inoue, Hiroyuki Tenmei, Yoshihide Yamaguchi, Noriyuki Oroku, Hiroshi Hozoji, Shigeharu Tsunoda, Madoka Minagawa, Naoya Kanda, Ichiro Anjo, Asao Nishimura, Akira Yajima, Kenji Ujiie
  • Patent number: 6624504
    Abstract: A semiconductor apparatus includes a semiconductor device having circuit electrodes aligned centrally of the semiconductor apparatus. A first electrically insulating layer is formed on said semiconductor device with said circuit electrodes being exposed from said first insulating layer. A second electrically insulating layer is formed on said first insulating layer, and external connection terminals are formed on said second insulating layer. A wiring is formed on said second insulating layer to electrically connect said external connect terminals to said circuit electrodes of said semiconductor device, and a third electrically insulating layer is formed on said second insulating layer and on said wiring. Particles are provided in the second insulating layer to control a shape of said second insulating layer.
    Type: Grant
    Filed: October 30, 2000
    Date of Patent: September 23, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Kosuke Inoue, Hiroyuki Tenmei, Yoshihide Yamaguchi, Noriyuki Oroku, Hiroshi Hozoji, Shigeharu Tsunoda, Madoka Minagawa, Naoya Kanda, Ichiro Anjo, Asao Nishimura, Akira Yajima, Kenji Ujiie
  • Patent number: 6610934
    Abstract: A multi-chip module including semiconductor devices and a wiring substrate for mounting the semiconductor devices in which the wiring substrate comprises a glass substrate having holes formed by sand blasting and a wiring layer formed on the surface of the glass substrate and having wiring and an insulation layer.
    Type: Grant
    Filed: November 29, 2001
    Date of Patent: August 26, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Yoshihide Yamaguchi, Takao Terabayashi, Hiroyuki Tenmei, Hiroshi Hozoji, Naoya Kanda
  • Patent number: 6589802
    Abstract: The present invention a structure in which a semiconductor integrated circuit chip can be easily removed and the reliability of flip-chip bonding is assured, a method of packaging electronic parts, and method and apparatus for detaching electronic parts. According to the invention, the object is achieved by a flip-chip bonding structure using two kinds of soluble and insoluble resins for bonding a semiconductor integrated circuit chip and a circuit board.
    Type: Grant
    Filed: August 18, 2000
    Date of Patent: July 8, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Toyoki Asada, Yuji Fujita, Kie Ueda, Naoya Kanda, Mari Matsuyoshi
  • Publication number: 20030109079
    Abstract: In the re-wiring formation process of a WLCSP, at least some of the re-wiring lines 3 that connect the bonding pads 1 and bump pads 2 of the semiconductor chips are formed using a photolithographic process that does not use a photomask. In this re-wiring formation process, standard portions are formed by development following photomask exposure, and portions that are to be designed corresponding to customer specifications are subjected to additional development following additional maskless exposure in the final stage.
    Type: Application
    Filed: July 30, 2002
    Publication date: June 12, 2003
    Inventors: Yoshihide Yamaguchi, Hiroyuki Tenmei, Hiroshi Hozoji, Naoya Kanda
  • Publication number: 20030071331
    Abstract: A semiconductor device which includes a semiconductor chip, an insulating film formed on the semiconductor chip, a plurality of projected stress relaxation materials formed on the insulating film, projected electrodes covering at least tops of the stress relaxation materials, and wiring lines for electrically connecting the projected electrodes and element electrodes of the semiconductor chip.
    Type: Application
    Filed: October 17, 2002
    Publication date: April 17, 2003
    Inventors: Yoshihide Yamaguchi, Shigeharu Tsunoda, Hiroyuki Tenmei, Hiroshi Hozoji, Naoya Kanda