Patents by Inventor Naoya Kanda

Naoya Kanda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020180015
    Abstract: A multi-chip module including semiconductor devices and a wiring substrate for mounting the semiconductor devices in which the wiring substrate comprises a glass substrate having holes formed by sand blasting and a wiring layer formed on the surface of the glass substrate and having wiring and an insulation layer.
    Type: Application
    Filed: November 30, 2001
    Publication date: December 5, 2002
    Inventors: Yoshihide Yamaguchi, Takao Terabayashi, Hiroyuki Tenmei, Hiroshi Hozoji, Naoya Kanda
  • Publication number: 20020180027
    Abstract: A multi-chip module including semiconductor devices and a wiring substrate for mounting the semiconductor devices in which the wiring substrate comprises a glass substrate having holes formed by sand blasting and a wiring layer formed on the surface of the glass substrate and having wiring and an insulation layer.
    Type: Application
    Filed: November 29, 2001
    Publication date: December 5, 2002
    Inventors: Yoshihide Yamaguchi, Takao Terabayashi, Hiroyuki Tenmei, Hiroshi Hozoji, Naoya Kanda
  • Publication number: 20020079575
    Abstract: A semiconductor module, comprising a wiring substrate on which wiring is formed, a semiconductor device electrically connected to the wiring formed on the wiring substrate, and an external connection terminal arranged on the semiconductor device mounted side of the wiring substrate so as to be a connected portion between the wiring and the outside electrically connected thereto, wherein there is formed an insulating resin layer thicker than the semiconductor device between the wiring substrate and the external connection terminal.
    Type: Application
    Filed: August 16, 2001
    Publication date: June 27, 2002
    Inventors: Hiroshi Hozoji, Yoshihide Yamaguchi, Naoya Kanda, Shigeharu Tunoda, Hiroyuki Tenmei
  • Publication number: 20020063332
    Abstract: The object of the present invention is to realize a semiconductor device enabling a flip chip connection without use of underfill.
    Type: Application
    Filed: March 20, 2001
    Publication date: May 30, 2002
    Inventors: Yoshihide Yamaguchi, Hiroyuki Tenmei, Kosuke Inoue, Noriyuki Oroku, Hiroshi Hozoji, Shigeharu Tsunoda, Naoya Kanda, Madoka Minagawa, Ichiro Anjo, Asao Nishimura, Kenji Ujiie, Akira Yajima
  • Patent number: 6153938
    Abstract: A stable low-connecting resistance connection arrangement having a high yield rate without using any special material or process for a substrate. A flip-chip connecting structure in which the semiconductor integrated circuit (IC) chip is mounted directly on an organic circuit substrate. To achieve reliable connection and low-connecting resistance, the present invention absorbs variation of the heights of projecting electrodes formed on a semiconductor IC chip and substrate electrodes of an organic circuit substrate for example, by deforming the substrate electrodes and/or substrate layer of the organic circuit substrate. Resin of a conductive paste disposed between the projecting electrodes and substrate electrodes is squeezed out leaving a high density conductive particle layer to lower a contact resistance between such electrodes.
    Type: Grant
    Filed: July 27, 1998
    Date of Patent: November 28, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Naoya Kanda, Toyoki Asada, Yoshio Oozeki, Yasuo Amano, Kunio Matsumoto, Yasuhiro Narikawa
  • Patent number: 5811877
    Abstract: An ultra-thin resin molded semiconductor device of high reliability with low cost and with easy repair at time of mounting. A plurality of these semiconductor devices are stacked to provide a semiconductor module which has a higher function than semiconductor devices in the same volume, and a card type module utilizing assembled by the stacked semiconductor module is provided. In manufacturing the semiconductor module, an extremely thin lead frame and an LSI chip are directly connected together, and the mirror surface of the LSI chip is exposed by using a low viscosity epoxy resin to have a thin molding. The mirror surface is grinded to have a further thin thickness of the whole structure of the semiconductor device. A part of the lead frame is formed as a reinforcing member, a heat radiation path, a light shielding part for shielding the LSI from harmful light beams, or a positioning base for mounting a substrate.
    Type: Grant
    Filed: March 31, 1997
    Date of Patent: September 22, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Ichiro Miyano, Ikuo Kawaguchi, Kunio Matsumoto, Junichi Saeki, Tooru Yoshida, Naoya Kanda, Isamu Yoshida, Michifumi Kawai, Hideo Yamakura, Shigeharu Tsunoda, Ritsuro Orihashi, Masachika Masuda, Sueo Kawai
  • Patent number: 5476726
    Abstract: A solder bonding metal layer which is formed on a circuit board comprises a metal layer having a mixture of first metal which is easily wetted with metals constituting the solder and which easily forms alloy or intermetallic compounds and of second metal which is not wetted easily with the above solder and not melted. In this case, a concentration gradient that the concentration of the first metal is high on the bonding surface may be formed in the metal layer. A circuit board having a solder bonding metal layer which keeps good bonding even after many times of repairs and improves the reliability is realized.
    Type: Grant
    Filed: January 19, 1993
    Date of Patent: December 19, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Masahide Harada, Akihiro Ando, Ryohei Satoh, Akira Yabushita, Naoya Kanda, Kazuhiko Horikoshi
  • Patent number: 5202151
    Abstract: The present invention relates to an electroless gold plating solution, a method of plating by using the same, and an electronic device plated with gold by using the same.According to the present electroless gold plating solution, the plating solution components contain no cyanide ions, the amount of a reducing agent used is small, and gold plating can be carried out without causing the gold plating on conducting paths having a fine interval between them to short-circuit the conducting paths.Therefore, according to the method of gold plating by using said electroless gold plating solution, a plating method that is safe in the plating work and in the treatment of its waste liquor can be accomplished. The method has a feature that the method can provide an electronic device on which parts can be mounted highly densely, and wherein the joint reliability to the parts is high.
    Type: Grant
    Filed: June 4, 1990
    Date of Patent: April 13, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Jiro Ushio, Osamu Miyazawa, Akira Tomizawa, Hitoshi Yokono, Naoya Kanda, Naoko Matsuura, Setsuo Ando, Hiroaki Okudaira
  • Patent number: 5191624
    Abstract: An optical waveguide is comprised of an optical substrate and an optical thin-film optical waveguide layer and formed such that ##EQU1## where .theta. is an output angle, n.sub.o1 is an ordinary refractive index of the optical substrate for an ordinary beam, n.sub.e1 is an extraordinary refractive index of the optical substrate for an extraordinary beam, n.sub.o2 is an ordinary refractive index of the optical thin-film optical waveguide layer for the ordinary beam and n.sub.e2 is an extraordinary refractive index of the optical thin-film optical waveguide layer for the extraordinary beam, and an electrode for generating a surface acoustic wave for diffracting light is formed on the optical waveguide to construct a collinear optical deflector.
    Type: Grant
    Filed: September 19, 1991
    Date of Patent: March 2, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Kenchi Ito, Kazumi Kawamoto, Naoya Kanda, Yasuo Hira, Hidemi Sato, Atsuko Fukushima, Masataka Shiba, Akira Inagaki, Minoru Yoshida
  • Patent number: 5178738
    Abstract: An ion-beam sputtering apparatus using an insulator target and a method for operating the same which is characterized by interposing a conductor film forming process during the ion beam processings using the insulator target. This conductor film formation prevents undesired charge build up on the inside of the apparatus and prevents undesired occurrence of abnormal discharge in the ion beam processing using an insulator as a target.
    Type: Grant
    Filed: May 10, 1991
    Date of Patent: January 12, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Yasushi Ishikawa, Naoya Kanda, Akio Fujiwara
  • Patent number: 5089104
    Abstract: Ion beams drawn out of a plurality of ion beam sources or neutralized beams derived therefrom are projected to a plurality of targets, and sputtered particles discharged from the targets are directed to a substrate. The composition of sputtered particles is measured in the vicinity to the substrate. The measured coomposition is compared with the predetermined reference value and the composition of sputtered particles is controlled based on the result of measurement. sputtered particles having a controlled composition distribution are deposited on the substrate thereby to form a multiple-element thin film.
    Type: Grant
    Filed: December 3, 1990
    Date of Patent: February 18, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Naoya Kanda, Yasushi Ishikawa, Kunio Matsumoto, Hiroshi Asao
  • Patent number: 5086337
    Abstract: This invention relates to a connecting structure for electrically connecting an electronic part such as an LSI chip to a substrate, its production method and an electronic device using the former. The present invention is particularly useful for connecting electrically a plurality of chips, for which an absorption function of the difference of thermal expansion in a horizontal direction and capability of displacement in a vertical direction are requisite, to a substrate. Moreover, the connecting structure of the present invention can simplify the fabrication process, has high reliability and can be applied to high performance electronic appliances and apparatuses such as electronic computers.
    Type: Grant
    Filed: September 13, 1988
    Date of Patent: February 4, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Takanobu Noro, Kunio Matsumoto, Muneo Oshima, Naoya Kanda, Suguru Sakaguchi, Akira Murata
  • Patent number: 4963974
    Abstract: The present invention relates to an electroless gold plating solution, a method of plating by using the same, and an electronic device plated with gold by using the same.According to the present electroless gold plating solution, the plating solution components contain no cyanide ions, the amount of a reducing agent used is small, and gold plating can be carried out without causing the gold plating on conducting paths having a fine interval between them to short-circuit the conducting paths.Therefore, according to the method of gold plating by using said electroless gold plating solution, a plating method that is safe in the plating work and in the treatment of its waste liquor can be accomplished. The method has a feature that the method can provide an electronic device on which parts can be mounted highly densely, and wherein the joint reliability to the parts is high.
    Type: Grant
    Filed: April 20, 1988
    Date of Patent: October 16, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Jiro Ushio, Osamu Miyazawa, Akira Tomizawa, Hitoshi Yokono, Naoya Kanda, Naoko Matsuura, Setsuo Ando, Hiroaki Okudaira
  • Patent number: 4935285
    Abstract: A ceramic substrate for densely integrated semiconductor arrays which is superior in a coefficient of thermal expansion, dielectric constant, strength of metallized bond, and mechanical strength, comprising a sintered body composed essentially of mullite crystals and a non-crystralline binder composed of SiO.sub.2, Al.sub.2 O.sub.3, and MgO, is provided.
    Type: Grant
    Filed: December 6, 1988
    Date of Patent: June 19, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Gyozo Toda, Takashi Kuroki, Shousaku Ishihara, Naoya Kanda, Tsuyoshi Fujita
  • Patent number: 4922377
    Abstract: This invention relates to a module which mounts a plurality of semiconductor devices and to a module substrate that interconnect the semiconductor devices.This invention has the testing and engineering change pads on the underside of the substrate. This arrangement results in the advantages of: providing a sufficient area for the testing and engineering change pads; improving the package density of semiconductor devices, which in turn leads to higher computation speed; and eliminating the need for a special cooling system during the module testing, simplifying the process of testing. Furthermore, since the signal joint terminals to the semiconductor chips are provided on the surface of the substrate on which the semiconductor chips are mounted and since the power bus joint terminals are provided around the chips on the semiconductor chip-mounting surface of the substrate, it is possible to realize a high density package with high reliability.
    Type: Grant
    Filed: November 16, 1988
    Date of Patent: May 1, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Kunio Matsumoto, Takanobu Noro, Naoya Kanda
  • Patent number: 4913769
    Abstract: The present invention relates to an element comprising a superconductive material or a wiring formation technique. In a thin film wiring board in which a superconductive material is used as a conductor, annealing should be conducted at a high temperature in an oxygen atmosphere after formation of a film in order to convert the conductor portion into a superconductive material, which makes it necessary to use an inorganic oxide as the insulating film. This brought about a problem that the etching of the second and subsequent insulation layers causes a damage to the wiring and insulation layer provided thereunder.In the present invention, an over-etching preventing layer is provided on a wiring layer provided under the second and subsequent insulation layers in order to solve the problem in question.The present invention brings about an effect of realizing the formation of a multi-layered wiring layer by making use of a superconductive material.
    Type: Grant
    Filed: August 4, 1988
    Date of Patent: April 3, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Naoya Kanda, Takayoshi Sowa, Tetsuya Yamazaki, Hiroaki Okudaira
  • Patent number: 4817276
    Abstract: A ceramic substrate for densely integrated semiconductor arrays which is superior in a coefficient of thermal expansion, dielectric constant, strength of metallized bond, and mechanical strength, comprising a sintered body composed essentially of mullite crystals and a non-crystalline binder composed of SiO.sub.2, Al.sub.2 O.sub.3, and MgO, is provided.
    Type: Grant
    Filed: April 2, 1986
    Date of Patent: April 4, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Gyozo Toda, Takashi Kuroki, Shousaku Ishihara, Naoya Kanda, Tsuyoshi Fujita
  • Patent number: 4734233
    Abstract: A ceramic wiring substrate and a process for producing the same having a conductive layer, obtained by sintering a conductive paste comprising 85 to 97% by weight of a tungsten powder and 15 to 3% by weight of a sintering additive (for conductive metal) having a specified composition, on a mullite ceramic substrate.
    Type: Grant
    Filed: January 27, 1987
    Date of Patent: March 29, 1988
    Assignee: Hitachi, Ltd.
    Inventors: Gyozo Toda, Takashi Kuroki, Shousaku Ishihara, Tsuyoshi Fujita, Naoya Kanda
  • Patent number: 4220592
    Abstract: A substituted acetonitrile such as .alpha.-isopropyl-p-chlorophenylacetonitrile is hydrolyzed using an acid to produce the corresponding substituted phenylacetic acid such as .alpha.-isopropyl-p-chlorophenylacetic acid in such a manner that, in a lot in any one hydrolysis reaction, (1) the hydrolysis is carried out in at least two steps, (2) an acid to be used in a subsequent first reaction step is a waste acid produced in a previous second reaction step and the subsequent reaction step(s) thereof if any, and (3) an acid to be used in a second reaction step and the subsequent reaction step(s) if any, is the waste acid produced in a previous second reaction step and subsequent reaction step(s), respectively, and a fresh acid.
    Type: Grant
    Filed: July 10, 1978
    Date of Patent: September 2, 1980
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Keiji Kagawa, Naoya Kanda, Fujio Masuko, Hirotoshi Nakanishi