Abstract: Apparatuses, methods, and articles of manufacture are disclosed. An example apparatus includes processor circuitry to assign a location value hyperdimensional vector (HDV) to a location in an image of a first patch of one or more pixels, assign at least a first channel HDV to the first patch, determine at least one pixel intensity value HDV for each of the one or more pixels in the first patch, bind together each of the pixel intensity value HDVs into at least one patch intensity value HDV, bind together the at least first channel HDV and the at least one patch intensity value HDV to produce a patch consensus intensity HDV, and generate a first hyperdimensional representation patch value HDV of the first patch by binding together at least a combination of the patch consensus intensity HDV and the location value HDV.

Abstract: Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

Abstract: A spiking neuromorphic network may be used to solve an optimization problem. The network may include primary neurons. The state of a primary neuron may be a value of a corresponding variable of the optimization problem. The primary neurons may update their states and change values of the variables. The network may also include a cost neuron that can compute, using a cost function, costs based on values of the variables sent to the cost neuron in the form of spikes from the primary neurons. The network may also include a minima neuron for determining the lowest cost and an integrator neuron for tracking how many computational steps the primary neurons have performed. The minima neuron or integrator neuron may determine whether convergence is achieved. After the convergence is achieved, the minima neuron or integrator neuron may instruct the primary neurons to stop computing new values of the variables.

Abstract: An integrated circuit (IC) package apparatus is disclosed. The IC package includes one or more processing units and a bridge, mounted below the one or more processing unit, including one or more arithmetic logic units (ALUs) to perform atomic operations.

Abstract: In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.

Abstract: Apparatuses, methods, and articles of manufacture are disclosed. An example apparatus includes processor circuitry to assign a location value hyperdimensional vector (HDV) to a location in an image of a first patch of one or more pixels, assign at least a first channel HDV to the first patch, determine at least one pixel intensity value HDV for each of the one or more pixels in the first patch, bind together each of the pixel intensity value HDVs into at least one patch intensity value HDV, bind together the at least first channel HDV and the at least one patch intensity value HDV to produce a patch consensus intensity HDV, and generate a first hyperdimensional representation patch value HDV of the first patch by binding together at least a combination of the patch consensus intensity HDV and the location value HDV.

Abstract: One embodiment provides a parallel processor comprising a hardware scheduler to schedule pipeline commands for compute operations to one or more of multiple types of compute units, a plurality of processing resources including a first sparse compute unit configured for input at a first level of sparsity and hybrid memory circuitry including a memory controller, a memory interface, and a second sparse compute unit configured for input at a second level of sparsity that is greater than the first level of sparsity.

Abstract: In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.

Abstract: An integrated circuit (IC) package apparatus is disclosed. The IC package includes one or more processing units and a bridge, mounted below the one or more processing unit, including one or more arithmetic logic units (ALUs) to perform atomic operations.

Abstract: Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

Abstract: One embodiment provides for a compute apparatus to perform machine learning operations, the compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction, the decoded instruction to cause the compute apparatus to perform a complex compute operation.

Abstract: Techniques and mechanisms for providing a logical state machine with a spiking neural network which includes multiple sets of nodes. Each of the multiple sets of nodes is to implement a different respective state, and each of the multiple spike trains is provided to respective nodes of each of the multiple sets of nodes. A given state of the logical state machine is implemented by configuring respective activation modes of each node of the corresponding set of nodes. The activation mode of a given node enables that node to signal, responsive to its corresponding spike train, that a respective state transition of the logical state machine is to be performed. In another embodiment, the multiple spike trains each represent a different respective character in a system used by data evaluated with the spiking neural network.

Abstract: Techniques and mechanisms for processing differential video data with a spiking neural network to provide action recognition functionality. In an embodiment, the spiking neural network is coupled to receive and process a first one or more spike trains which represent an encoded version of a sequence comprising frames of differential video data. In turn, the frames of differential video data are each based on a difference between a respective two frames of raw video data. Based on the processing of the first one or more spike trains, the spiking neural network may output a second one or more spike trains. In another embodiment, the second one or more spike trains are provided to train the spiked neural network to recognize an activity type, or to classify a video sequence as including a representation of an instance of the activity type.

Abstract: Techniques and mechanisms for servicing a search query using a spiking neural network. In an embodiment, a spiking neural network receives an indication of a first context of the search query, wherein a set of nodes of the spiking neural network each correspond to a respective entry of a repository. One or more nodes of the set of nodes are each excited to provide a respective cyclical response based on the first context, wherein a first cyclical response is by a first node. Due at least in part to a coupling of the excited nodes, a perturbance signal, based on a second context of the search query, results in a change of the first resonance response relative to one or more other resonance responses. In another embodiment, data corresponding to the first node is selected, based on the change, as an at least partial result of the search query.

Abstract: An apparatus to facilitate compute compression is disclosed. The apparatus includes a graphics processing unit including mapping logic to map a first block of integer pixel data to a compression block and compression logic to compress the compression block.

Abstract: In an example, an apparatus comprises a plurality of processing unit cores, a plurality of cache memory modules associated with the plurality of processing unit cores, and a machine learning model communicatively coupled to the plurality of processing unit cores, wherein the plurality of cache memory modules share cache coherency data with the machine learning model. Other embodiments are also disclosed and claimed.

Abstract: A mechanism is described for facilitating storage management for machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting one or more components associated with machine learning, where the one or more components include memory and a processor coupled to the memory, and where the processor includes a graphics processor. The method may further include allocating a storage portion of the memory and a hardware portion of the processor to a machine learning training set, where the storage and hardware portions are precise for implementation and processing of the training set.

Abstract: Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

Abstract: Techniques and mechanisms for determining the value of a weight associated with a synapse of a spiking neural network. In an embodiment, a first spike train and a second spike train are output, respectively, by a first node and a second node of the spiking neural network, wherein the synapse is coupled between said nodes. The weight is applied to signaling communicated via the synapse. A value of the weight is updated based on a product of a first value and a second value, wherein the first value is based on a first rate of spiking by the first spike train, and the second value is based on a second rate of spiking by the second spike train. In another embodiment, the weight is updated based on a product of a derivative of the first rate of spiking and a derivative of the second rate of spiking.

Abstract: An integrated circuit (IC) package apparatus is disclosed. The IC package includes one or more processing units and a bridge, mounted below the one or more processing unit, including one or more arithmetic logic units (ALUs) to perform atomic operations.