Patents by Inventor Narayan Srinivasa

Narayan Srinivasa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210035255
    Abstract: One embodiment provides for a compute apparatus to perform machine learning operations, the compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction, the decoded instruction to cause the compute apparatus to perform a complex machine learning compute operation.
    Type: Application
    Filed: July 14, 2020
    Publication date: February 4, 2021
    Applicant: Intel Corporation
    Inventors: Eriko Nurvitadhi, Balaji Vembu, Nicolas C. Galoppo Von Borries, Rajkishore Barik, Tsung-Han Lin, Kamal Sinha, Nadathur Rajagopalan Satish, Jeremy Bottleson, Farshad Akhbari, Altug Koker, Narayan Srinivasa, Dukhwan Kim, Sara S. Baghsorkhi, Justin E. Gottschlich, Feng Chen, Elmoustapha Ould-Ahmed-Vall, Kevin Nealis, Xiaoming Chen, Anbang Yao
  • Patent number: 10902547
    Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a plurality of processing units each comprising a plurality of execution units (EUs), wherein the plurality of EUs comprise a first EU type and a second EU type.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: January 26, 2021
    Assignee: Intel Corporation
    Inventors: Prasoonkumar Surti, Narayan Srinivasa, Feng Chen, Joydeep Ray, Ben J. Ashbaugh, Nicolas C. Galoppo Von Borries, Eriko Nurvitadhi, Balaji Vembu, Tsung-Han Lin, Kamal Sinha, Rajkishore Barik, Sara S. Baghsorkhi, Justin E. Gottschlich, Altug Koker, Nadathur Rajagopalan Satish, Farshad Akhbari, Dukhwan Kim, Wenyin Fu, Travis T. Schluessler, Josh B. Mastronarde, Linda L. Hurd, John H. Feit, Jeffery S. Boles, Adam T. Lake, Karthik Vaidyanathan, Devan Burke, Subramaniam Maiyuran, Abhishek R. Appu
  • Patent number: 10885425
    Abstract: A spiking neural network (SNN) includes artificial neurons interconnected by artificial synapses to model a particular network. A first neuron emits spikes to neighboring neurons to cause a wave of spikes to propagate through the SNN. Weights of a portion of the synapses are increased responsive to the wave of spikes based on a spike timing dependent plasticity (STDP) rule. A second neuron emits spike to cause a chain of spikes to propagate to the first neuron on a path based on the increase in the synaptic weights. The path is determined to represent a shortest path in the particular network from a first network node represented by the second neuron to a second network node represented by the first neuron.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Nabil Imam, Narayan Srinivasa
  • Patent number: 10871966
    Abstract: A mechanism is described for facilitating intelligent dispatching and vectorizing at autonomous machines. A method of embodiments, as described herein, includes detecting a plurality of threads corresponding to a plurality of workloads associated with tasks relating to a graphics processor. The method may further include determining a first set of threads of the plurality of threads that are similar to each other or have adjacent surfaces, and physically clustering the first set of threads close together using a first set of adjacent compute blocks.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: December 22, 2020
    Assignee: INTEL CORPORATION
    Inventors: Feng Chen, Narayan Srinivasa, Abhishek R. Appu, Altug Koker, Kamal Sinha, Balaji Vembu, Joydeep Ray, Nicolas C. Galoppo Von Borries, Prasoonkumar Surti, Ben J. Ashbaugh, Sanjeev Jahagirdar, Vasanth Ranganathan
  • Patent number: 10846590
    Abstract: A spike timing dependent plasticity (STDP) rule is applied in a spiking neural network (SNN) that includes artificial synapses bi-directionally connecting artificial neurons in the SNN to model locations within a physical environment. A first neuron is activated to cause a spike wave to propagate from the first neuron to other neurons in the SNN. Propagation of the spike wave causes synaptic weights of a subset of the synapses to be increased based on the STDP rule. A second neuron is activated after propagation of the spike wave to cause a spike chain to propagate along a path from the second neuron to the first neuron, based on the changes to the synaptic weights. A physical path is determined from the second to the first neuron based on the spike chain, and a signal may be sent to a controller of an autonomous device to cause the autonomous to navigate the physical path.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Nabil Imam, Narayan Srinivasa
  • Patent number: 10846595
    Abstract: Various systems and methods for implementing unsupervised or reinforcement learning operations for a neuron weight used in a neural network are described. In an example, the learning operations include processing a spike train input at a neuron of a spiking neural network, applying a synaptic weight, and observing spike events occurring before and after the neuron processing based on respective spike traces. A synaptic weight update process operates to generate a new value of the synaptic weight based upon the spike traces, configuration values, and a reference weight value. A reference weight update process also operates to generate a new value of the reference value for significant changes to the synaptic weight. Reinforcement may be provided in some examples to implement changes to the reference weight in reduced time. In some examples, the techniques may be implemented in a neuromorphic hardware implementation of the spiking neural network.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Andreas Wild, Narayan Srinivasa
  • Publication number: 20200364822
    Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a mixed precision core to perform a mixed precision multi-dimensional matrix multiply and accumulate operation on 8-bit and/or 32 bit signed or unsigned integer elements.
    Type: Application
    Filed: August 3, 2020
    Publication date: November 19, 2020
    Applicant: Intel Corporation
    Inventors: Abhishek R. Appu, Altug Koker, Linda L. Hurd, Dukhwan Kim, Mike B. Macpherson, John C. Weast, Feng Chen, Farshad Akhbari, Narayan Srinivasa, Nadathur Rajagopalan Satish, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Anbang Yao, Tatiana Shpeisman
  • Patent number: 10824871
    Abstract: Described is a system and method for generating a unique signature for a space. During operation, the system causes a mobile platform to make one or more passes through the space along a repeatable path. While moving through the space, the system captures an image of the space around the mobile platform. A filter is applied to the image to generate vertical bins, the vertical bins being one-dimensional vectors of the space around the mobile platform. The one-dimensional vectors are combined over time to create a two-dimensional trace, with the two-dimensional trace being a unique signature for the space.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: November 3, 2020
    Assignee: HRL Laboratories, LLC
    Inventors: Corey M. Thibeault, Narayan Srinivasa
  • Publication number: 20200342321
    Abstract: Techniques and mechanisms for performing a Bayesian inference with a spiking neural network. In an embodiment, a parent node of the spiking neural network receives a first bias signal which is periodic. The parent node communicates a likelihood signal to a child node, wherein the parent node and the child node correspond to a first condition and a second condition, respectively. Based on a phase change which is applied to the first bias signal, the likelihood signal indicates a probability of the first condition. The child node also receives a signal which indicates an instance of the second condition. Based on the indication and a second bias signal, the child node signals to the first node that an adjustment is to be made to the phase change applied to the first bias signal. After the adjustment, the likelihood signal indicates an updated probability of the first condition.
    Type: Application
    Filed: February 23, 2018
    Publication date: October 29, 2020
    Applicant: Intel Corporation
    Inventors: Arnab Paul, Narayan Srinivasa
  • Patent number: 10769748
    Abstract: One embodiment provides for a compute apparatus to perform machine learning operations, the compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction, the decoded instruction to cause the compute apparatus to perform a complex machine learning compute operation.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: September 8, 2020
    Assignee: Intel Corporation
    Inventors: Eriko Nurvitadhi, Balaji Vembu, Nicolas C. Galoppo Von Borries, Rajkishore Barik, Tsung-Han Lin, Kamal Sinha, Nadathur Rajagopalan Satish, Jeremy Bottleson, Farshad Akhbari, Altug Koker, Narayan Srinivasa, Dukhwan Kim, Sara S. Baghsorkhi, Justin E. Gottschlich, Feng Chen, Elmoustapha Ould-Ahmed-Vall, Kevin Nealis, Xiaoming Chen, Anbang Yao
  • Publication number: 20200272884
    Abstract: Techniques and mechanisms for servicing a search query using a spiking neural network. In an embodiment, a spiking neural network receives an indication of a first context of the search query, wherein a set of nodes of the spiking neural network each correspond to a respective entry of a repository. One or more nodes of the set of nodes are each excited to provide a respective cyclical response based on the first context, wherein a first cyclical response is by a first node. Due at least in part to a coupling of the excited nodes, a perturbance signal, based on a second context of the search query, results in a change of the first resonance response relative to one or more other resonance responses. In another embodiment, data corresponding to the first node is selected, based on the change, as an at least partial result of the search query.
    Type: Application
    Filed: December 15, 2017
    Publication date: August 27, 2020
    Applicant: INTEL CORPORATION
    Inventors: Arnab PAUL, Narayan SRINIVASA
  • Publication number: 20200272883
    Abstract: Techniques and mechanisms to update a synaptic weight of a spiking neural network which is trained to provide a decision of a decision-making sequence. In an embodiment, a synapse of the spiking neural network is associated with a weight which is to be given to communications via that given synapse. The spiking neural network generates output signaling, indicating a decision to the decision-making process, which is evaluated to determine whether, according to predefined test criteria, the decision-making process is successful or unsuccessful. One or more nodes of the spiking neural network receive a reward/penalty signal which is based on the evaluation. In response to the reward/penalty signal indicating a reward event or a penalty event, a synaptic weight value is updated. In another embodiment, input signaling provided to the spiking neural network represents a sub-sequence of two or more most recent states in a sequence of states.
    Type: Application
    Filed: December 19, 2017
    Publication date: August 27, 2020
    Applicant: INTEL COPORATION
    Inventors: Yongqiang CAO, Andreas WILD, Narayan SRINIVASA
  • Publication number: 20200272815
    Abstract: Techniques and mechanisms to facilitate a data classification functionality by communicating feedback signals with a spiked neural network. In an embodiment, input signaling, provided to the spiking neural network, results in one or more output spike trains which are indicative of that the input signaling corresponds to a particular data type. Based on the one or more output spike trains, feedback signals are variously communicated each to a respective node of the spiking neural network. The feedback signals variously control signal response characteristics of the nodes. Subsequent output signaling by the spiking neural network, in further response the input signaling, is improved based on the feedback control of nodes' signal responses. In another embodiment, the feedback signals are used to adjust synaptic weight values during training of the spiking neural network.
    Type: Application
    Filed: December 19, 2017
    Publication date: August 27, 2020
    Applicant: INTEL CORPORATION
    Inventors: Yongqiang CAO, Narayan SRINIVASA
  • Publication number: 20200265290
    Abstract: Techniques and mechanisms for providing a logical state machine with a spiking neural network which includes multiple sets of nodes. Each of the multiple sets of nodes is to implement a different respective state, and each of the multiple spike trains is provided to respective nodes of each of the multiple sets of nodes. A given state of the logical state machine is implemented by configuring respective activation modes of each node of the corresponding set of nodes. The activation mode of a given node enables that node to signal, responsive to its corresponding spike train, that a respective state transition of the logical state machine is to be performed. In another embodiment, the multiple spike trains each represent a different respective character in a system used by data evaluated with the spiking neural network.
    Type: Application
    Filed: December 15, 2017
    Publication date: August 20, 2020
    Applicant: Intel Corporation
    Inventors: Arnab Paul, Narayan Srinivasa
  • Patent number: 10726337
    Abstract: In a method for emulation of neuromorphic hardware on a computer processor, the neuromorphic hardware including computing circuits, the computing circuits including neurons and synapses connecting the neurons, the neurons being configured to communicate to each other through the synapses via spikes, the computing circuits being configured to execute in parallel in increments of time, the method includes, for each said time increment, emulating processing of the synapses, emulating processing of the neurons, and recording by the processor the next ones of the spikes for a subset of the neurons on a non-transitory physical medium. The processing of the synapses includes receiving previous ones of the spikes at presynaptic ends of the synapses, and transmitting the received previous ones of the spikes to postsynaptic ends of the synapses. The processing of the neurons includes receiving current ones of the spikes and generating next ones of the spikes.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: July 28, 2020
    Assignee: HRL Laboratories, LLC
    Inventors: Corey M. Thibeault, Narayan Srinivasa
  • Publication number: 20200226096
    Abstract: An integrated circuit (IC) package apparatus is disclosed. The IC package includes one or more processing units and a bridge, mounted below the one or more processing unit, including one or more arithmetic logic units (ALUs) to perform atomic operations.
    Type: Application
    Filed: January 16, 2020
    Publication date: July 16, 2020
    Applicant: Intel Corporation
    Inventors: Altug Koker, Farshad Akhbari, Feng Chen, Dukhwan Kim, Narayan Srinivasa, Nadathur Rajagopalan Satish, Liwei Ma, Jeremy Bottleson, Eriko Nurvitadhi, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Tatiana Shpeisman, Abhishek R. Appu
  • Publication number: 20200218977
    Abstract: Techniques and mechanisms for determining the value of a weight associated with a synapse of a spiking neural network. In an embodiment, a first spike train and a second spike train are output, respectively, by a first node and a second node of the spiking neural network, wherein the synapse is coupled between said nodes. The weight is applied to signaling communicated via the synapse. A value of the weight is updated based on a product of a first value and a second value, wherein the first value is based on a first rate of spiking by the first spike train, and the second value is based on a second rate of spiking by the second spike train. In another embodiment, the weight is updated based on a product of a derivative of the first rate of spiking and a derivative of the second rate of spiking.
    Type: Application
    Filed: December 19, 2017
    Publication date: July 9, 2020
    Applicant: INTEL CORPORATION
    Inventors: Arnab PAUL, Narayan SRINIVASA
  • Publication number: 20200218959
    Abstract: Techniques and mechanisms for processing differential video data with a spiking neural network to provide action recognition functionality. In an embodiment, the spiking neural network is coupled to receive and process a first one or more spike trains which represent an encoded version of a sequence comprising frames of differential video data. In turn, the frames of differential video data are each based on a difference between a respective two frames of raw video data. Based on the processing of the first one or more spike trains, the spiking neural network may output a second one or more spike trains. In another embodiment, the second one or more spike trains are provided to train the spiked neural network to recognize an activity type, or to classify a video sequence as including a representation of an instance of the activity type.
    Type: Application
    Filed: December 19, 2017
    Publication date: July 9, 2020
    Applicant: Intel Corporation
    Inventor: Narayan Srinivasa
  • Publication number: 20200210338
    Abstract: In an example, an apparatus comprises a plurality of processing unit cores, a plurality of cache memory modules associated with the plurality of processing unit cores, and a machine learning model communicatively coupled to the plurality of processing unit cores, wherein the plurality of cache memory modules share cache coherency data with the machine learning model. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 26, 2019
    Publication date: July 2, 2020
    Applicant: Intel Corporation
    Inventors: Chandrasekaran Sakthivel, Prasoonkumar Surti, John C. Weast, Sara S. Baghsorkhi, Justin E. Gottschlich, Abhishek R. Appu, Nicolas C. Galoppo Von Borries, Joydeep Ray, Narayan Srinivasa, Feng Chen, Ben J. Ashbaugh, Rajkishore Barik, Tsung-Han Lin, Kamal Sinha, Eriko Nurvitadhi, Balaji Vembu, Altug Koker
  • Patent number: 10679118
    Abstract: A spiking neural network (SNN) is defined that includes artificial neurons interconnected by artificial synapses, the SNN defined to correspond to one or more numerical matrices in an equation such that weight values of the synapses correspond to values in the numerical matrices. An input vector is provided to the SNN to correspond to a numerical vector in the equation. A steady state spiking rate is determined for at least a portion of the neurons in the SNN and an approximate result of a matrix inverse problem corresponding to the equation is determined based on values of the steady state spiking rates.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: June 9, 2020
    Assignee: Intel Corporation
    Inventors: Tsung-Han Lin, Narayan Srinivasa