Patents by Inventor Narendra Singh

Narendra Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150306526
    Abstract: A filter assembly for fluid filtration having a push-activated lock and release mechanism. A push filter design activates a floating key lock upon insertion and extraction, where the filter key may be used simultaneously as a lock and as an identifier for particular filter attributes. The filter base may be situated inline, and in fluid communication, with influent and effluent piping, such as within a refrigerator. The filter housing assembly may be attached to, and removed from, the filter base by a push-actuated release. Upon insertion, the filter key shifts the filter lock longitudinally to receive interlocking segments. Upon extraction, the same axial push shifts the filter lock further to align the interlocking fingers within gaps that allow for easy extraction. The specific key lock design allows a user to identify and match certain filter configurations received by the mechanical support, and reject other filter configurations.
    Type: Application
    Filed: July 16, 2015
    Publication date: October 29, 2015
    Inventors: Stephen P. Huda, Michael J. Sherman, Steven J. Haehn, Erik R. Klimpel, Sathyanarayana Jujaray, Vivek Kunwar Narendra Singh
  • Patent number: 9119162
    Abstract: A method and apparatus for extending the driving capacity of a power management device are provided. The method involves determining an energy requirement for the operation of a power management device. Next, the method compares the energy requirement for the operation of a power management device with a capability of a first power device. If the energy requirement is greater than the energy requirement of the first power device, the energy is switched to a second power device of higher capacity. The apparatus includes: a first power device; a second power device connected in parallel to the first power device; a first inductor connected to the first power device and a capacitor connected to the first inductor; and a second inductor connected to a second power device and a capacitor connected to the second inductor.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: August 25, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Adrian M Stenzel, Todd R Sutton, Narendra Singh Mehta, Siegfried W Breitmeier, Gordon P Lee
  • Patent number: 9095822
    Abstract: We report an electro-deionization (EDI) device having split flow arrangement for the purification of second pass RO permeate water with high flow rate in which the feed water is fed through the center port and is diverted into each section of dilute chamber with equal flow rate, producing two product streams. The EDI device has concentrate chambers adjacent to dilute chambers in two sections of the stack, allowing independent flow through the separate sections. The split flow design reduces resin bed depth requirement for processing of second pass RO permeate water. This results in higher flow rate through the stack, elimination of the pressure drop limitation, and reduction of power consumption per unit volume of water.
    Type: Grant
    Filed: October 3, 2011
    Date of Patent: August 4, 2015
    Assignee: AQUATECH INTERNATIONAL CORPORATION
    Inventors: Ravi Chidambaran, Narendra Singh Bisht, Pavan Raina
  • Patent number: 8901989
    Abstract: An adaptive gate drive circuit that can generate a gate bias voltage with temperature compensation for a MOSFET is disclosed. The adaptive gate drive circuit may generate the gate bias voltage with variable drive capability to combat higher gate leakage current of the MOSFET at higher temperature. In one design, an apparatus includes a control circuit and a gate drive circuit. The control circuit generates at least one control signal having a variable frequency determined based on a sensed temperature of the MOSFET. For example, a clock divider ratio may be determined based on the sensed temperature of the MOSFET, an input clock signal may be divided based on the clock divider ratio to obtain a variable clock signal, and the control signal(s) may be generated based on the variable clock signal. The gate drive circuit generates a bias voltage for the MOSFET based on the control signal(s).
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 2, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Narendra Singh Mehta, Lennart Karl-Axel Mathe
  • Patent number: 8859377
    Abstract: A method for fabricating a transistor on a semiconductor wafer includes providing a partial transistor containing a gate stack, extension regions, and source/drain sidewalls. The method also includes performing a source/drain implant of the semiconductor wafer, forming a cap layer over the semiconductor wafer, and performing a source/drain anneal. In addition, the method includes performing a damage implant of the cap layer and removing the cap layer over the semiconductor wafer.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: October 14, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Mahalingam Nandakumar, Wayne Bather, Narendra Singh Mehta
  • Publication number: 20140266011
    Abstract: An electronic device is described. The electronic device includes a first port. The electronic device also includes a second port. The electronic device further includes a multiphase charger. The multiphase charger includes a first buck. The multiphase charger also includes a second buck. The multiphase charger further includes a first port switch. The multiphase charger also includes a second port switch. The multiphase charger further includes a reverse boost switch. The multiphase charger also includes a multiphase switch.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventors: Narendra Singh Mehta, Chris M. Rosolowski, Sandeep Chaman Dhar, Todd R. Sutton
  • Publication number: 20140235299
    Abstract: A method and apparatus for extending the driving capacity of a power management device are provided. The method involves determining an energy requirement for the operation of a power management device. Next, the method compares the energy requirement for the operation of a power management device with a capability of a first power device. If the energy requirement is greater than the energy requirement of the first power device, the energy is switched to a second power device of higher capacity. The apparatus includes: a first power device; a second power device connected in parallel to the first power device; a first inductor connected to the first power device and a capacitor connected to the first inductor; and a second inductor connected to a second power device and a capacitor connected to the second inductor.
    Type: Application
    Filed: February 19, 2013
    Publication date: August 21, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventors: Adrian M. Stenzel, Todd R. Sutton, Narendra Singh Mehta, Siegfried W. Breitmeier, Gordon P. Lee
  • Publication number: 20140028357
    Abstract: An adaptive gate drive circuit that can generate a gate bias voltage with temperature compensation for a MOSFET is disclosed. The adaptive gate drive circuit may generate the gate bias voltage with variable drive capability to combat higher gate leakage current of the MOSFET at higher temperature. In one design, an apparatus includes a control circuit and a gate drive circuit. The control circuit generates at least one control signal having a variable frequency determined based on a sensed temperature of the MOSFET. For example, a clock divider ratio may be determined based on the sensed temperature of the MOSFET, an input clock signal may be divided based on the clock divider ratio to obtain a variable clock signal, and the control signal(s) may be generated based on the variable clock signal. The gate drive circuit generates a bias voltage for the MOSFET based on the control signal(s).
    Type: Application
    Filed: March 15, 2013
    Publication date: January 30, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Narendra Singh Mehta, Lennart Karl-Axel Mathe
  • Publication number: 20130240442
    Abstract: We provide a process for treatment of produced water, including but not limited to water produced by a “steam flood” process for extraction of oil from oil sands, including the removal of color from the water. This removal may be accomplished through addition of color-removal polymers and flocculents. This process may also be useful for other water treatment processes including reverse osmosis and filtration.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 19, 2013
    Inventors: Ravi Chidambaran, Narendra Singh Bisht, Pavan Raina
  • Publication number: 20130193077
    Abstract: We provide a process for the neutralization and precipitation of high pH brines that eliminates the formation of “gelatinous silica” during neutralization. The high pH brine is neutralized in a two-step neutralization process. In the first step the salt concentration of a high pH brine is built up to a minimum level of 8-12%, and then its pH is reduced to 9-9.5. The partially neutralized brine is allowed a reaction period with mild agitation. Subsequently the pH is further reduced, typically to 8-9. A coagulant and/or a polymer can also be used to enhance the settling or filtration rate of the neutralized stream.
    Type: Application
    Filed: July 30, 2012
    Publication date: August 1, 2013
    Inventors: Ravi Chidambaran, Pavan Raina, Narendra Singh Bisht
  • Patent number: 8451797
    Abstract: A mobile node includes a processor, a network interface, and a storage device having computer program code for execution by the processor. The computer program code includes a network layer for transmitting and receiving packets and an intermediate driver that transmits packets to the network layer and receives packets from the network layer using a virtual interne protocol (IP) address to identify the mobile node. The intermediate driver transmits packets to the network interface and receives packets from the network interface using a routable actual IP address to identify the mobile node. The intermediate driver permits the actual IP address to change when the mobile node moves from a first subnet to a second subnet without a corresponding change in the virtual IP address. A corresponding NAT associates the virtual IP address with a second actual IP address when the NAT is notified that the mobile node is in the second subnet.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: May 28, 2013
    Assignee: Alcaltel Lucent
    Inventors: Milind M. Buddhikot, Adiseshu Hari, Scott C. Miller, Kundan Narendra Singh
  • Publication number: 20120224057
    Abstract: A method and apparatus is provided that includes techniques for providing complete solutions for role-based, rules-driven access enforcement, the techniques including situational awareness and video surveillance. An embodiment addresses blended risk assessment and security across logical systems, IT applications, databases, and physical systems from a single analytic dashboard, with auto-remediation capabilities. Further, an embodiment provides capability and functionality for co-relating seemingly innocent events and activities to detect real threats and risks, while providing powerful alerting and automated remedial action strategies for decisive action.
    Type: Application
    Filed: March 6, 2012
    Publication date: September 6, 2012
    Inventors: Jasvir Singh GILL, Inderpal Ricky Arora, Srinivasa Kakkera, Subrat Narendra Singh
  • Publication number: 20120080314
    Abstract: We report an electro-deionization (EDI) device having split flow arrangement for the purification of second pass RO permeate water with high flow rate in which the feed water is fed through the center port and is diverted into each section of dilute chamber with equal flow rate, producing two product streams. The EDI device has concentrate chambers adjacent to dilute chambers in two sections of the stack, allowing independent flow through the separate sections. The split flow design reduces resin bed depth requirement for processing of second pass RO permeate water. This results in higher flow rate through the stack, elimination of the pressure drop limitation, and reduction of power consumption per unit volume of water.
    Type: Application
    Filed: October 3, 2011
    Publication date: April 5, 2012
    Inventors: Ravi Chidambaran, Narendra Singh Bisht, Pavan Raina
  • Publication number: 20110318782
    Abstract: Disclosed herein are recombinant tobacco osmotin polypeptides and methods for expressing tobacco osmotin polypeptides in microbial host cells. The recombinant tobacco osmotin polypeptides produced by the methods disclosed herein may be utilized as biocides or as therapeutic agents in medicaments.
    Type: Application
    Filed: December 17, 2010
    Publication date: December 29, 2011
    Applicant: AUBURN UNIVERSITY
    Inventors: Tung-Shi Huang, Ywh-Min Tzou, Narendra Singh, Bryan A. Chin
  • Patent number: 7838370
    Abstract: A method for manufacturing an isolation structure is disclosed that protects the isolation structure during etching of a dichlorosilane (DCS) nitride layer. The method involves the formation of a bis-(t-butylamino)silane-based nitride liner layer within the isolation trench, which exhibits a five-fold greater resistance to nitride etching solutions as compared with DCS nitride, thereby allowing protection against damage from unintended over-etching. The bis-(t-butylamino)silane-based nitride layer also exerts a greater tensile strain on moat regions that results in heightened carrier mobility of active regions, thereby increasing the performance of NMOS transistors embedded therein.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: November 23, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Narendra Singh Mehta, Wayne Anthony Bather, Ajith Varghese
  • Publication number: 20100270622
    Abstract: The present invention provides a method for manufacturing a semiconductor device as well as a semiconductor device. The method, among other steps, may include forming a gate structure over a substrate, and forming a strain inducing sidewall spacer proximate a sidewall of the gate structure, the strain inducing sidewall configured to introduce strain in a channel region below the gate structure.
    Type: Application
    Filed: July 7, 2010
    Publication date: October 28, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mahalingam NANDAKUMAR, Wayne A. BATHER, Narendra Singh MEHTA, Lahir Shaik ADAM
  • Publication number: 20100252887
    Abstract: A method for fabricating a transistor on a semiconductor wafer includes providing a partial transistor containing a gate stack, extension regions, and source/drain sidewalls. The method also includes performing a source/drain implant of the semiconductor wafer, forming a cap layer over the semiconductor wafer, and performing a source/drain anneal. In addition, the method includes performing a damage implant of the cap layer and removing the cap layer over the semiconductor wafer.
    Type: Application
    Filed: June 17, 2010
    Publication date: October 7, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mahalingam Nandakumar, Wayne Bather, Narendra Singh Mehta
  • Patent number: 7772094
    Abstract: A method for semiconductor processing is provided, wherein a removal of one or more layers is aided by structurally weakening the one or more layers via ion implantation. A semiconductor substrate is provided having one or more primary layers formed thereon, and a secondary layer is formed over the one or more primary layers. One or more ion species are implanted into the secondary layer, therein structurally weakening the secondary layer, and a patterned photoresist layer is formed over the secondary layer. Respective portions of the secondary layer and the one or more primary layers that are not covered by the patterned photoresist layer are removed, and the patterned photoresist layer is further removed. At least another portion of the secondary layer is removed, wherein the structural weakening of the secondary layer increases a removal rate of the at least another portion of the secondary layer.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: August 10, 2010
    Assignee: Texas Instuments Incorporated
    Inventors: Mahalingam Nandakumar, Wayne Bather, Narendra Singh Mehta
  • Patent number: 7705061
    Abstract: This invention presents an ion exchange media including a plurality of cation exchange zones and anion exchange zones in flow paths that are contained in a substantially nonporous resin transport framework. During electrodeionization and other potential applications the ion exchange media of the invention prevents unfavorable water splitting at resin-membrane interfaces and encourages water splitting at resin-resin interfaces where the water splitting may be constructively used to regenerate the resin.
    Type: Grant
    Filed: December 11, 2006
    Date of Patent: April 27, 2010
    Assignee: Aquatech International Corporation
    Inventors: Ravi Chidambaran, Pavan Raina, Devesh Sharma, Narendra Singh Bisht
  • Patent number: 7696021
    Abstract: A method of manufacturing a semiconductor device including calibrating an ion implant process. The calibration includes forming a dielectric layer over a calibration substrate. A dopant is implanted into the dielectric layer. Charge is deposited on a surface of the dielectric layer, and voltage on the surface is measured. An electrical characteristic of the dielectric layer is determined, and a doping level of the dielectric layer is determined from the electrical characteristic. The electrical characteristic is associated with an operating set-point of the ion implant process. The calibrated ion implant process is used to implant the dopant into a semiconductor substrate.
    Type: Grant
    Filed: November 13, 2006
    Date of Patent: April 13, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Narendra Singh Mehta, Ajith Varghese, Benjamin Moser