Patents by Inventor Naresh Kumar

Naresh Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200362198
    Abstract: An acid chemical mechanical polishing composition polishes silicon nitride over silicon dioxide and simultaneously inhibits damage to the silicon dioxide. The acid chemical mechanical polishing composition includes polyvinylpyrrolidone polymers, anionic functional colloidal silica abrasive particles and an amine carboxylic acid. The pH of the acid chemical mechanical polishing composition is 5 or less.
    Type: Application
    Filed: May 16, 2019
    Publication date: November 19, 2020
    Inventors: Naresh Kumar Penta, Kwadwo E. Tettey, Matthew Van Hanehem
  • Patent number: 10822524
    Abstract: The present invention provides aqueous chemical mechanical planarization (CMP) polishing compositions that comprise a mixture of (a) one or more alkoxylated diamines having a number average molecular weight (Mn) of from 1,000 to 20,000, or, preferably, from 1000-15000 and having four (poly)alkoxy ether groups each containing from 5 to 100 alkoxy repeat units; (b) from 0.01 to 2 wt. % or, preferably, from 0.1 to 1.5 wt. %, as solids, based on the total weight of the compositions, of one or more aqueous dispersions of elongated, bent or nodular colloidal silica particles, preferably, having a secondary particle size as determined by dynamic light scattering (DLS) of from 20 to 60 nm; and (c) ammonia or an amine base, wherein the compositions have a pH ranging from 9 to 11. The compositions are substantially free of metals, such as alkali or alkaline earth metals that can damage substrates in polishing.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: November 3, 2020
    Assignee: ROHM AND HAAS ELECTRONIC MATERIALS CMP HOLDINGS, I
    Inventors: Naresh Kumar Penta, Matthew Van Hanehem, Kwadwo E. Tettey, Koichi Yoshida, Kyohei Yoshida
  • Publication number: 20200344311
    Abstract: The current invention discloses a method for managing a multi-tenant server enclosure comprising a plurality of resources including a plurality of compute servers, storage modules, and network interfaces. The method comprises defining a first virtual enclosure template for provisioning a virtual enclosure for a tenant, the virtual enclosure includes a plurality of resources comprising one or more compute servers, one or more storage modules and one or more network interfaces from the plurality of compute servers, storage modules and network interfaces; and creating a first virtual enclosure dedicated to a first tenant and a second virtual enclosure dedicated to a second tenant based on the virtual enclosure template, wherein a plurality of resources of the first virtual enclosure are physically distinct from a plurality of resources of the second virtual enclosure.
    Type: Application
    Filed: March 19, 2020
    Publication date: October 29, 2020
    Inventors: Krishna Mouli Tankala, Murali Krishna Chippagiri, Naresh Kumar Panthangi
  • Patent number: 10787592
    Abstract: Acid chemical mechanical polishing compositions and methods have enhanced defect inhibition and selectively polish silicon nitride over silicon dioxide in an acid environment. The acid chemical mechanic polishing compositions include poly(2-ethyl-2-oxazoline) polymers, anionic functional colloidal silica particles, amine carboxylic acids and have a pH of 5 or less.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: September 29, 2020
    Assignee: Rohm and Haas Electronic Materials CMP Holdings, I
    Inventors: Naresh Kumar Penta, Kwadwo E. Tettey, Matthew Van Hanehem
  • Patent number: 10783300
    Abstract: The present disclosure relates to a system for performing static timing analysis in an electronic design. Embodiments may include providing, using at least one processor, an electronic design and extracting hierarchical crossing path exception information from a hierarchical design view associated with the electronic design. Embodiments may further include transferring the hierarchical crossing path exception information to a block view associated with the electronic design and extracting a timing model based upon, at least in part, the hierarchical crossing path exception information. Embodiments may also include implementing the timing model at a top-level view associated with the electronic design.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: September 22, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Sushobhit Singh, Naresh Kumar, Beenish, Ankur Gulati, Vishal Karda, Shashank Prasad
  • Patent number: 10776547
    Abstract: A static timing analysis system for finding timing violations in a digital circuit design prior to circuit fabrication, and associated methods, use infinite-depth path-based analysis (IPBA) to achieve reduced pessimism as opposed to systems or methods employing only graph-based analysis (GBA), but with greatly reduced compute time requirements, or greater logic path coverage, versus systems or methods employing conventional or exhaustive path-based analysis. IPBA achieves the improved coverage or compute time results by slotting nodes of a circuit design graph into stages, propagating phases stage-by-stage for all paths in parallel, and merging phases wherever possible during the analysis.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: September 15, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Umesh Gupta, Naresh Kumar, Prashant Sethia, Ritika Govila, Jayant Sharma
  • Publication number: 20200265337
    Abstract: A method for machine learning based prediction of at least one subsequent UI layout is provided. The method may include detecting, by the electronic device, a first transition event. Further, the method may include identifying, by the electronic device, a UI layout associated with a first application of the electronic device. Further, the method may include predicting, by the electronic device, the at least one subsequent UI layout to be displayed based on at least one transition parameter, wherein the at least one subsequent UI layout is associated with at least one of the first application or at least one second application. Further, the method may include loading, by the electronic device, the at least one subsequent UI layout in a memory of the electronic device.
    Type: Application
    Filed: February 14, 2020
    Publication date: August 20, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sripurna MUTALIK, Nidhal Kottamoola IBRAHIMKUTTY, Naresh Kumar NARASIMMA MOORTHY, Manith SHETTY, Anuradha KANUKOTLA, Jaeho KIM, Kwanjin JUNG, Wonseo CHOI
  • Publication number: 20200259792
    Abstract: Cloud-based Intrusion Prevention Systems (IPS) include receiving traffic associated with a user of a plurality of users, wherein each user is associated with a customer of a plurality of customers for a cloud-based security system, and wherein the traffic is between the user and the Internet; analyzing the traffic based on a set of signatures including stream-based signatures and security patterns; blocking the traffic responsive to a match of a signature of the set of signatures; and performing one or more of providing an alert based on the blocking and updating a log based on the blocking.
    Type: Application
    Filed: April 27, 2020
    Publication date: August 13, 2020
    Inventors: Srikanth Devarajan, Sushil Pangeni, Vladimir Stepanenko, Ravinder Verma, Naresh kumar Povlavaram Munirathnam
  • Publication number: 20200250163
    Abstract: Index sharding in a low-latency database analysis system includes obtaining index configuration data for indexing constituent data, the constituent data including a plurality of logical tables, and indexing, by an indexing unit, the constituent data by partitioning the constituent data based on a characteristic of the constituent data into at least a first partition and a second partition, segmenting the first partition into a first segment of the first partition, sharding the first segment into a first shard of the first segment of the first partition, segmenting, using hash-partitioning, the second partition into one or more segments of the second partition, and for each segment of the second partition, sharding the segment into one or more respective shards.
    Type: Application
    Filed: August 30, 2019
    Publication date: August 6, 2020
    Inventors: Peter Kuimelis, Naresh Kumar, Satyam Shekhar, Amit Prakash, Abhishek Rai
  • Patent number: 10711158
    Abstract: The present invention provides aqueous chemical mechanical planarization polishing (CMP polishing) compositions, such as for semiconductor substrates, comprising an abrasive of one or more dispersions of elongated, bent or nodular colloidal silica particles which contain a cationic nitrogen atom, and one or more amine carboxylic acids having an isoelectric point (pI) below 5, preferably, acidic amine carboxylic acids or pyridine acids, wherein the compositions have a pH of from 2 to 5. The compositions enable polishing at a high oxide:nitride removal rate ratio.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: July 14, 2020
    Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.
    Inventors: Naresh Kumar Penta, Zifeng Li
  • Publication number: 20200210323
    Abstract: Systems, methods, and computer program products for testing new software are provided. Multiple payloads that correspond to scenarios in a production computing environment are identified. From the multiple payloads unique payloads are identified. User data that corresponds to the unique payloads is created. A first testing environment conducts a test using software components in the production environment, the unique payloads, and the user data to generate expected results. A second testing environment conducts a test using new software that replaces at least one of the software components in the production environment, the unique payloads, and the user data, to generate actual results. The one or more attributes in the expected results are compared to the one or more attributes in the actual results to determine if the new software causes an error.
    Type: Application
    Filed: December 31, 2018
    Publication date: July 2, 2020
    Inventors: Prasanth Kuricheti, Jogendar Singh, Rajesh Kumar, Xinran Fang, Naresh Kumar Paturi, Durjay Kumar Mishra, Anil Kumar Kandru, Venkata Siva Sai Manepalli
  • Patent number: 10686904
    Abstract: An alert notification is received and evaluated by a processor. An identifier of a subscriber who is registered to receive the first alert notification is identified. The subscriber identifier is used to select assessment rules corresponding to the first alert notification. The assessment rules are applied to the alert notification to determine whether the receipt of the alert notification satisfies a condition for taking one or more actions. If the condition is met, one or more commands are issued to effectuate the one or more actions.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: June 16, 2020
    Assignee: Time Warner Cable Enterprises LLC
    Inventor: Naresh Kumar
  • Patent number: 10662841
    Abstract: Embodiments of emission reduction system including various embodiments of an emission filters for a power plant including a gas turbine are disclosed. The system includes: an emission filter; and a retraction system operably coupled to an exhaust passage of the gas turbine. The exhaust passage defines an exhaust path of exhaust from the gas turbine. The retraction system selectively moves the emission filter between a first location within the exhaust path and a second location out of the exhaust path. In a combined cycle power plant, the first location is upstream of a heat recovery steam generator (HRSG). The systems and filters described allow for temporary positioning of emission filter(s) just downstream of a gas turbine exhaust outlet, or upstream of an HRSG, where provided, for emission reduction at low loads or startup conditions, and removal of the emission filter(s) once operations move to higher loads.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: May 26, 2020
    Assignee: General Electric Company
    Inventors: Parag Prakash Kulkarni, Naresh Kumar Amineni, Lewis Berkley Davis, Jr., Gordon Raymond Smith
  • Patent number: 10655518
    Abstract: Embodiments of emission reduction system including various embodiments of an emission filters for a power plant including a gas turbine are disclosed. The system includes: an emission filter; and a retraction system operably coupled to an exhaust passage of the gas turbine. The exhaust passage defines an exhaust path of exhaust from the gas turbine. The retraction system selectively moves the emission filter between a first location within the exhaust path and a second location out of the exhaust path. In a combined cycle power plant, the first location is upstream of a heat recovery steam generator (HRSG). The systems and filters described allow for temporary positioning of emission filter(s) just downstream of a gas turbine exhaust outlet, or upstream of an HRSG, where provided, for emission reduction at low loads or startup conditions, and removal of the emission filter(s) once operations move to higher loads.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: May 19, 2020
    Assignee: General Electric Company
    Inventors: Parag Prakash Kulkarni, Naresh Kumar Amineni, Lewis Berkley Davis, Jr., Gordon Raymond Smith
  • Publication number: 20200151154
    Abstract: A method and system may be implemented for automatically analyzing data in a database. A method for use in a low-latency database analysis system may include generating a schema. The schema may be based on a portion of an external database. The method may include storing the schema in an in-memory database. The method may include receiving a data-query. The method may include generating a resolved-request. The resolved-request may be based on the data-query and the stored schema. The stored schema may be used for executing the query on the external database. The method may include receiving results data responsive to the data-query from the external database. The method may include outputting the results data for display on a user interface.
    Type: Application
    Filed: November 12, 2019
    Publication date: May 14, 2020
    Inventors: Sandeep Kumar, Siva Singaram, Rakesh Kothari, Naresh Kumar, Jasmeet Singh Jaggi, Manikanta Balakavi, Tushar Mahale, Rahul Paliwal
  • Publication number: 20200151166
    Abstract: Improved systems and methods for database analysis are described herein. A method includes generating a graph-based ontological data structure including nodes connected by edges in a low-latency database analysis system, wherein each node represents a respective analytical-object in the low-latency database analysis system, maintaining versions for each of the nodes in the graph-based ontological data structure, maintaining versions for each of the edges in the graph-based ontological data structure, maintaining a transaction log for each transaction with respect to the graph-based ontological data structure, reverting to an earlier version of at least a portion of the graph-based ontological data structure using the transaction log, versioned nodes, and versioned edges in response to an event, and outputting a version of the graph-based ontological data structure in a defined form for presentation to a user or for use by a client.
    Type: Application
    Filed: November 13, 2019
    Publication date: May 14, 2020
    Inventors: Satyam Shekhar, Naresh Kumar, Nitish Rajguru, Mayank Raj, Priyendra Singh Deshwal
  • Patent number: 10626298
    Abstract: Chemical mechanical polishing compositions contain polyethoxylated amines, phosphoric acid or salts thereof, and positively charged nitrogen containing colloidal silica abrasive particles. The chemical mechanical polishing compositions are used in polishing methods for suppressing the removal rate of amorphous silicon while maintaining tunable oxide to silicon nitride removal rate ratios. The chemical mechanical polishing compositions can be used in front-end-of line semiconductor processing.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: April 21, 2020
    Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.
    Inventors: Naresh Kumar Penta, Kwadwo E. Tettey, Matthew Van Hanehem
  • Patent number: 10611865
    Abstract: The present invention provides a solid organomagnesium precursor having formula {Mg(OR?)X}.a{MgX2}.b{Mg(OR?)2}.c{R?OH}, wherein R? is selected from a hydrocarbon group, X is selected from a halide group, and a:b:c is in range of 0.01-0.5:0.01-0.5:0.01-5 and process for preparing the same, said process comprising contacting a magnesium source with a solvating agent, an organohalide and an alcohol to obtain the solid organomagnesium precursor. The present invention also provides a process for preparing a catalyst system using the organomagnesium precursor and its use thereof for polymerization of olefins.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: April 7, 2020
    Assignee: INDIAN OIL CORPORATION LIMITED
    Inventors: Sukhdeep Kaur, Gurmeet Singh, Bhasker Bantu, Naresh Kumar, Gurpreet Singh Kapur, Shashi Kant, Biswajit Basu, Ravinder Kumar Malhotra
  • Publication number: 20200102478
    Abstract: A chemical mechanical polishing composition for polishing silicon dioxide over silicon nitride includes certain acidic heterocyclic nitrogen compounds having a pK value of 5 of less. Also, methods for polishing a substrate to remove some of the silicon dioxide and silicon nitride are disclosed.
    Type: Application
    Filed: September 25, 2019
    Publication date: April 2, 2020
    Inventors: Naresh Kumar Penta, Robert L. Auger
  • Publication number: 20200104152
    Abstract: In one aspect, a computerized method includes the step of providing a first virtual machine on first server. The method includes the step of, with the first virtual machine, communicating a network traffic to a second virtual machine on a second server using a virtual network identified with a virtual local area network (VLAN). The method includes the step of, with a virtual function (VF) on a physical network interface controller (pNIC) of the second server, assigning to the VLAN to a specified VF. The method includes the step of, sending a data packet is sent out of the pNIC towards a TOR switch, wherein the TOR switch has the VLAN enabled and other user specific policies configured. The method includes the step of, sending the data packet to a second TOR switch. The method includes the step of, with the second TOR switch, sending the data packet towards the pNIC on the second server based on a destination the second virtual machine's MAC address.
    Type: Application
    Filed: March 18, 2019
    Publication date: April 2, 2020
    Inventors: SRINIVAS VEGESNA, JAYAPRAKASH KUMAR, PRAMOD VENKATESH, NARESH KUMAR THUKKANI